PIC16F87-I/SS Microchip Technology, PIC16F87-I/SS Datasheet - Page 73

• Manufacturer Part Number: PIC16F87-I/SS
• Description: IC MCU FLASH 4KX14 EEPROM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F87-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2
1997 Microchip Technology Inc.
OSC2/CLKOUT
(RC mode)
Clocking Scheme/Instruction Cycle
OSC1
Q4
PC
Q2
Q3
Q1
The clock input (from OSC1) is internally divided by four to generate four non-overlapping
quadrature clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incre-
mented every Q1, and the instruction is fetched from the program memory and latched into the
instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow are illustrated in
Example
Figure 4-3: Clock/Instruction Cycle
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
T
4-1.
CY
PC
1
Q3
Q4
Q1
Execute INST (PC)
Fetch INST (PC+1)
Section 4. Architecture
Q2
T
PC+1
CY
2
Q3
Q4
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
T
PC+2
CY
3
Q3
Q4
DS31004A-page 4-5
Figure
Internal
phase
clock
4-3, and
4