DSPIC33FJ12GP202-I/ML Microchip Technology, DSPIC33FJ12GP202-I/ML Datasheet - Page 32

• Manufacturer Part Number: DSPIC33FJ12GP202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12GP202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33F
DS70155C-page 30
8.9
The UART is a full-duplex asynchronous system that
can communicate with peripheral devices, such as
personal computers, RS-232 and RS-485 interfaces.
The dsPIC33F devices have one or more UARTs.
The key features of the UART module are:
• Full-duplex operation with 8 or 9-bit data
• Even, odd or no parity options (for 8-bit data)
• One or two Stop bits
• Fully integrated Baud Rate Generator (BRG) with
• Baud rates range from up to 10 Mbps and down to
• 4-character deep transmit data buffer
• 4-character deep receive data buffer
• Parity, framing and buffer overrun error detection
• Full IrDA
• LIN bus support
• Support for interrupt on address detect (9th bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostics
The UART1 and UART2 modules support DMA data
transfers.
8.10
The I
for
microcontroller devices. These peripheral devices may
be serial EEPROMs, shift registers, display drivers, A/D
Converters, etc.
The Inter-Integrated Circuit (I
hardware support for both slave and multi-master
operations.
The key features of the I
• I
• I
• I
• Serial clock synchronization for I
• I
• Slew rate control for 100 kHz and 400 kHz bus speeds
16-bit prescaler
38 Hz at 40 MIPS
and decoding of IrDA
- Auto wake-up from Sleep or Idle mode on
- Auto-baud detection
- Break character support
- On transmission of 1 or 4 characters
- On reception of 1, 3 and 4 characters
master and slaves
used as a handshake mechanism to suspend and
resume serial transfer (serial clock stretching)
collision and will arbitrate accordingly
2
2
2
2
C slave operation supports 7 and 10-bit address
C master operation supports 7 and 10-bit address
C port allows bidirectional transfers between
C supports multi-master operation; detects bus
Start bit detect
2
communicating
C module is a synchronous serial interface, useful
UART Module
I
2
®
C™ Module
support, including hardware encoding
®
with
2
messages
C module are:
other
2
C) module offers full
2
C port can be
peripheral
Preliminary
or
In I
module will override the data direction bits for these pins.
8.11
The Controller Area Network (CAN) module is a serial
interface useful for communicating with other CAN
modules or microcontroller devices. This interface/
protocol was designed to allow communications within
noisy environments.
The CAN module is a communication controller
implementing the CAN 2.0 A/B protocol, as defined in
the BOSCH specification. The module supports
CAN 1.2, CAN 2.0A, CAN2.0B Passive and CAN 2.0B
Active versions of the protocol. Details of these protocols
can be found in the BOSCH CAN specification.
The CAN module features:
• Implementation of the CAN protocol CAN 1.2,
• Standard and extended data frames
• Data lengths of 0-8 bytes
• Programmable bit rate up to 1 Mbit/sec
• Automatic response to remote frames
• Up to 16 receive buffers in DMA RAM
• FIFO Buffer mode (up to 64 messages deep)
• 16 full (standard/extended identifier) acceptance
• 3 full acceptance filter masks
• Up to 8 transmit buffers in DMA RAM
• DMA can be used for transmission and reception
• Programmable wake-up functionality with
• Programmable Loopback mode supports self-test
• Signaling via interrupt capabilities for all CAN
• Programmable clock source
• Programmable link to timer module for
• Low-power Sleep and Idle mode
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
CAN 2.0A and CAN 2.0B
filters
integrated low-pass filter
operation
receiver and transmitter error states
time-stamping and network synchronization
2
C mode, pin SCL is clock and pin SDA is data. The
Controller Area Network (CAN)
Module
© 2005 Microchip Technology Inc.