DSPIC30F2010-20I/SO Microchip Technology, DSPIC30F2010-20I/SO Datasheet - Page 28

• Manufacturer Part Number: DSPIC30F2010-20I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/SOG; DSPIC30F201020IS

dsPIC30F2010
3.2.2
The X data space is used by all instructions and
supports all addressing modes. There are separate
read and write data buses. The X read data bus is the
return data path for all instructions that view data space
as combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports Modulo Addressing for
all
restrictions. Bit-Reversed addressing is only supported
for writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions
dedicates two W register pointers, W10 and W11, to
always address Y data space, independent of X data
space, whereas W8 and W9 always address X data
space. Note that during accumulator write-back, the
data address space is considered a combination of X
and Y data spaces, so the write occurs across the X
bus. Consequently, the write can be to any address in
the entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automated circular buffers. Of course, all other
instructions can access the Y data address space
through the X data path, as part of the composite linear
space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user
programmable. Should an EA point to data outside its
own assigned address space, or to a location outside
physical memory, an all-zero word/byte will be
returned. For example, although Y address space is
visible by all non-MAC instructions using any Address-
ing mode, an attempt by a MAC instruction to fetch data
from that space, using W8 or W9 (X space pointers),
will return 0x0000.
TABLE 3-2:
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70118H-page 28
Attempted Operation
EA = an unimplemented address
W8 or W9 used to access Y data
space in a MAC instruction
W10 or W11 used to access X
data space in a MAC instruction
instructions,
DATA SPACES
EFFECT OF INVALID
MEMORY ACCESSES
subject
to
addressing
Data Returned
0x0000
0x0000
0x0000
mode
3.2.3
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
To
PIC
usage efficiency, the dsPIC30F instruction set supports
both word and byte operations. Data is aligned in data
memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all
effective
generated by the DSP operations, which are
restricted to word-sized data) are internally scaled to
step through word-aligned memory. For example, the
core would recognize that Post-Modified Register
Indirect Addressing mode, [Ws ++], will result in a
value of Ws + 1 for byte operations and Ws + 2 for
word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. Should
a misaligned read or write be attempted, an address
error trap will be generated. If the error occurred on a
read, the instruction underway is completed, whereas if
it occurred on a write, the instruction will be executed
but the write will not occur. In either case, a trap will
then be executed, allowing the system and/or user to
examine the machine state prior to execution of the
address fault.
FIGURE 3-8:
®
0001
0003
0005
help
MCU devices and improve data space memory
15
address
DATA SPACE WIDTH
DATA ALIGNMENT
maintain
MSB
Byte 1
Byte 3
Byte 5
calculations
DATA ALIGNMENT
backward
© 2008 Microchip Technology Inc.
8 7
LSB
Byte 0
Byte 2
Byte 4
compatibility
(including
0
0000
0002
0004
those
with