PIC18F2450-I/SP Microchip Technology, PIC18F2450-I/SP Datasheet - Page 2

• Manufacturer Part Number: PIC18F2450-I/SP
• Description: IC PIC MCU FLASH 8KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2450-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 23
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2450/4450
2. Module: USB
REGISTER 14-5:
4. Module: USB
EXAMPLE 14-1:
DS80274A-page 2
bit 3
Assembly:
LOOP:
DONE
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF){UIRbits.ACTVIF = 0};
In Section 14.4.3 “BD Address Validation”, the
USB RAM address range described in the first
paragraph is 400h to 7FFh. The correct range is
400h to 4FFh.
In Section 14.5 “USB Interrupts”, the following
subsection
Section 14.5.1 “USB Interrupt Status Register
(UIR)”:
BCF
BTFSS
BRA
BCF
BRA
DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
0 = No data toggle synchronization is performed
is
except for a SETUP transaction, which is accepted even if the data toggle bits do not
match
UCON, SUSPND
UIR, ACTVIF
DONE
UIR, ACTVIF
LOOP
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), CPU MODE (PARTIAL REPRESENTATION)
CLEARING ACTVIF BIT (UIR<2>)
inserted
immediately
after
3. Module: USB
14.5.1.1
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend or while the
USB module is suspended. A few clock cycles are
required to synchronize the internal hardware state
machine before the ACTVIF bit can be cleared by
firmware. Clearing the ACTVIF bit before the internal
hardware is synchronized may not have an effect on
the value of ACTVIF. Additionally, if the USB module
uses the clock from the 96 MHz PLL source, then after
clearing the SUSPND bit, the USB module may not be
immediately operational while waiting for the 96 MHz
PLL to lock. The application code should clear the
ACTVIF bit as shown in Example 14-1.
In Register 14-5 (BDnSTAT, CPU Mode), the
operation of the DSTEN bit is clarified with
additional text, shown below in bold.
Bus Activity Detect Interrupt Bit
(ACTVIF)
© 2006 Microchip Technology Inc.