PIC18F2450-I/SP Microchip Technology, PIC18F2450-I/SP Datasheet - Page 136
PIC18F2450-I/SP
Manufacturer Part Number
PIC18F2450-I/SP
Description
IC PIC MCU FLASH 8KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2450-ISO.pdf
(324 pages)
3.PIC18F2450-ISO.pdf
(6 pages)
4.PIC18F2450-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(4 pages)
6.PIC18F2450-ISO.pdf
(4 pages)
7.PIC18F4450-IP.pdf
(322 pages)
Specifications of PIC18F2450-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
23
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163025 - PIC DEM FULL SPEED USB DEMO BRD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2450-ISO PDF datasheet #2
- PIC18F2450-ISO PDF datasheet #3
- PIC18F2450-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- PIC18F2450-ISO PDF datasheet #6
- PIC18F4450-IP PDF datasheet #7
- Current page: 136 of 322
- Download datasheet (6Mb)
PIC18F2450/4450
14.2.3
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 14-4).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
REGISTER 14-3:
DS39760C-page 134
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
bit 2
bit 1
bit 0
Note 1:
Note:
U-0
—
This bit is only valid for endpoints with available EVEN and ODD BD registers.
USB STATUS REGISTER (USTAT)
The data in the USB Status register is valid
only when the TRNIF interrupt flag is
asserted.
Unimplemented: Read as ‘0’
ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
....
0001 = Endpoint 1
0000 = Endpoint 0
DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
PPBI: Ping-Pong BD Pointer Indicator bit
1 = The last transaction was to the ODD BD bank
0 = The last transaction was to the EVEN BD bank
Unimplemented: Read as ‘0’
ENDP3
R-x
USTAT: USB STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
ENDP2
R-x
ENDP1
R-x
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ENDP0
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will immediately
reassert the interrupt. If no additional data is present,
TRNIF will remain clear; USTAT data will no longer be
reliable.
FIGURE 14-4:
R-x
Note:
4-Byte FIFO
for USTAT
Data Bus
If an endpoint request is received while the
USTAT
automatically issue a NAK back to the
host.
DIR
R-x
USTAT from SIE
FIFO
USTAT FIFO
© 2007 Microchip Technology Inc.
x = Bit is unknown
is
PPBI
R-x
full,
(1)
Clearing TRNIF
Advances FIFO
the
SIE
U-0
—
bit 0
will
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