PIC18F2450-I/ML Microchip Technology, PIC18F2450-I/ML Datasheet - Page 320

• Manufacturer Part Number: PIC18F2450-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2450-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: UART/USART, USB
• Number Of I /o: 23
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 768Byte
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 10
• Height: 0.88 mm
• Length: 6 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F2450/4450
Two-Speed Start-up ................................................. 191, 205
Two-Word Instructions
TXSTA Register
U
Universal Serial Bus ........................................................... 59
DS39760D-page 318
Example Cases .......................................................... 58
BRGH Bit ................................................................. 157
Address Register (UADDR) ..................................... 136
Associated Registers ............................................... 150
Buffer Descriptor Table ............................................ 137
Buffer Descriptors .................................................... 137
Class Specifications and Drivers ............................. 152
Descriptors ............................................................... 152
Endpoint Control ...................................................... 135
Enumeration ............................................................. 152
External Transceiver ................................................ 131
Eye Pattern Test Enable .......................................... 133
Firmware and Drivers ............................................... 150
Frame Number Registers ......................................... 136
Frames ..................................................................... 151
Internal Transceiver ................................................. 131
Internal Voltage Regulator ....................................... 133
Interrupts .................................................................. 143
Address Validation ........................................... 140
Assignment in Different
BDnSTAT Register (CPU Mode) ..................... 138
BDnSTAT Register (SIE Mode) ....................... 140
Byte Count ....................................................... 140
Example ........................................................... 137
Memory Map .................................................... 141
Ownership ........................................................ 137
Ping-Pong Buffering ......................................... 141
Register Summary ........................................... 142
Status and Configuration ................................. 137
and USB Transactions ..................................... 143
Buffering Modes ....................................... 142
USB
USB. See Universal Serial Bus.
W
Watchdog Timer (WDT) ........................................... 191, 203
WWW Address ................................................................ 319
WWW, On-Line Support ...................................................... 6
X
XORLW ............................................................................ 253
XORWF ........................................................................... 254
Layered Framework ................................................. 151
Oscillator Requirements .......................................... 150
Output Enable Monitor ............................................. 133
Overview .......................................................... 129, 151
Ping-Pong Buffer Configuration ............................... 133
Power ...................................................................... 151
Power Modes ........................................................... 149
Pull-up Resistors ...................................................... 133
RAM ......................................................................... 136
Speed ...................................................................... 152
Status and Control ................................................... 130
Status Register (USTAT) ......................................... 134
Transfer Types ......................................................... 151
UFRMH:UFRML Registers ...................................... 136
Internal Voltage Regulator Specifications ................ 281
Module Specifications .............................................. 281
Associated Registers ............................................... 204
Control Register ....................................................... 203
During Oscillator Failure .......................................... 206
Programming Considerations .................................. 203
Bus Power Only ............................................... 149
Dual Power with Self-Power
Self-Power Only ............................................... 149
Memory Map .................................................... 136
Dominance .............................................. 149
© 2008 Microchip Technology Inc.