DSPIC33FJ06GS202-I/SP Microchip Technology, DSPIC33FJ06GS202-I/SP Datasheet - Page 7

• Manufacturer Part Number: DSPIC33FJ06GS202-I/SP
• Description: IC DSPIC MCU/DSP 6K 28-DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ06GS202-I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 6KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9. Module: PWM
10. Module: Comparator
11. Module: ADC
© 2010 Microchip Technology Inc.
The PWM module fails to wake the CPU from
Sleep mode on a PWM fault event.
Work around
Use the external interrupt pins to wake the CPU
from Sleep mode.
Affected Silicon Revisions
If the slew rate of the Comparator input signal is
lower than 198 mV/µs, the Comparator module
generates erroneous triggers/interrupts.
Work around
The Slew rate of Comparator input signal must be
higher than 198 mV/µs to avoid multiple triggers/
interrupts.
Affected Silicon Revisions
Selecting the primary FRC (F
source for the ADC module by setting the
SLOWCLK bit (ADCON<12>) to the default setting
of ‘0’, does not work.
Work around
Always set the SLOWCLK bit (ADCON<12>) to ‘1’,
which selects the Auxiliary Clock (ACLK) as a
clock source for the ADC. Use the Auxiliary Clock
Configuration registers to select the primary FRC
(F
sources as inputs. See Section 8.0 “Oscillator
Configuration”
(DS70318) for more information.
Affected Silicon Revisions
A2
A2
A2
VCO
X
X
X
) as a source (if desired) or other clock
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
of
the
device
VCO
) as a clock
data
sheet
12. Module: Auxiliary Clock
13. Module: Comparator
14. Module: UART
When the PWMMD bit in the PMD1 register is set,
the Auxiliary Clock to both the ADC and PWM
modules is disabled.
Work around
To disable the Auxiliary clock for the PWM module
but not for the ADC module, set the individual
PWM generator PMD bits in the PMD6 register.
Affected Silicon Revisions
The comparator interrupt should be generated on
a rising edge of the comparator output. When
using the inverted polarity setting for the analog
comparator
interrupt should be generated when the analog
voltage at the comparator input falls below the
programmable threshold determined by the
CMPDAC register setting. However, with this
setting the interrupts may be generated regardless
of the state of the comparator.
Work around
When using comparator interrupts, configure the
external circuit to use the non-inverted polarity
comparator setting (CMPCONx<CMPPOL> = 0).
Affected Silicon Revisions
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
(CMPCONx<CMPPOL> = 1),
X
X
X
DS80439H-page 7
the