DSPIC30F2010-20I/MM Microchip Technology, DSPIC30F2010-20I/MM Datasheet - Page 94
![IC DSPIC MCU/DSP 12K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2010-20I/MM
Manufacturer Part Number
DSPIC30F2010-20I/MM
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2010-20ISO.pdf
(202 pages)
3.DSPIC30F2010-20ISO.pdf
(18 pages)
4.DSPIC30F2010-20ISO.pdf
(6 pages)
5.DSPIC30F2010-20ISO.pdf
(26 pages)
6.DSPIC30F2010-20IMM.pdf
(204 pages)
Specifications of DSPIC30F2010-20I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F2010-20I/MMG
DSPIC30F201020IMM
DSPIC30F201020IMM
DSPIC30F201020IMM
DSPIC30F201020IMM
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2010-20ISO PDF datasheet #2
- DSPIC30F2010-20ISO PDF datasheet #3
- DSPIC30F2010-20ISO PDF datasheet #4
- DSPIC30F2010-20ISO PDF datasheet #5
- DSPIC30F2010-20IMM PDF datasheet #6
- Current page: 94 of 204
- Download datasheet (3Mb)
dsPIC30F2010
15.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit FRMEN enables
framed SPI support and causes the SSx pin to perform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SSx
FIGURE 15-1:
FIGURE 15-2:
DS70118H-page 94
Note: x = 1 or 2, y = 1 or 2.
Note: x = 1 or 2.
Framed SPI Support
SDOx
SCKx
SDIx
SSx
MSb
PROCESSOR 1
SPI BLOCK DIAGRAM
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
SPI Master
SS & FSYNC
Shift Register
(SPIxBUF)
Control
(SPIxSR)
Receive
Read
SPIxBUF
bit 0
LSb
SPIxSR
Control
SDOx
SCKx
Clock
SDIx
clock
Shift
SPIxBUF
Write
Transmit
Serial Clock
Data Bus
Internal
Select
Edge
pin is an input or an output (i.e., whether the module
receives or generates the frame synchronization
pulse). The frame pulse is an active-high pulse for a
single SPI clock cycle. When frame synchronization is
enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
SDOy
SCKy
SDIy
Enable Master Clock
MSb
Secondary
Prescaler
1:1-1:8
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPIyBUF)
(SPIySR)
SPI Slave
© 2008 Microchip Technology Inc.
Prescaler
1:16, 1:64
1:1, 1:4,
Primary
LSb
F
CY
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