PIC18F67J11-I/PT Microchip Technology, PIC18F67J11-I/PT Datasheet - Page 444
![IC PIC MCU FLASH 64KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J11-I/PT
Manufacturer Part Number
PIC18F67J11-I/PT
Description
IC PIC MCU FLASH 64KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(448 pages)
3.DV164136.pdf
(4 pages)
4.PIC18F63J11-IPT.pdf
(36 pages)
5.PIC18F66J11-IPT.pdf
(4 pages)
6.PIC18F66J11-IPT.pdf
(4 pages)
7.PIC18F66J11-IPT.pdf
(20 pages)
Specifications of PIC18F67J11-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Ram Size
3930 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
15-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J11-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F67J11-I/PT
Manufacturer:
MICROCH
Quantity:
20 000
PIC18F87J11 FAMILY
DS39778D-page 444
I
I
I
I
MSSP I
MSSP I
Parallel Master Port Read ........................................ 410
Parallel Master Port Write ........................................ 411
Parallel Slave Port ................................................... 409
Parallel Slave Port Read .................................. 162, 165
Parallel Slave Port Write .................................. 162, 165
Program Memory Read ............................................ 405
Program Memory Write ............................................ 406
PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Dis-
PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart En-
PWM Direction Change ........................................... 216
PWM Direction Change at Near 100% Duty Cycle .. 216
PWM Output ............................................................ 202
Read and Write, 8-Bit Data, Demultiplexed Address 169
Read, 16-Bit Data, Demultiplexed Address ............. 172
Read, 16-Bit Muliplexed Data, Fully Multiplexed 16-Bit
Read, 16-Bit Multiplexed Data, Partially Multiplexed Ad-
Read, 8-Bit Data, Fully Multiplexed 16-Bit Address . 171
Read, 8-Bit Data, Partially Multiplexed Address ...... 169
Read, 8-Bit Data, Partially Multiplexed Address, Enable
Read, 8-Bit Data, Wait States Enabled, Partially Multi-
Repeated Start Condition ......................................... 258
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Send Break Character Sequence ............................ 286
Slave Synchronization ............................................. 229
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 228
SPI Mode (Slave Mode, CKE = 0) ........................... 230
SPI Mode (Slave Mode, CKE = 1) ........................... 230
Synchronous Reception (Master Mode, SREN) ...... 289
Synchronous Transmission ...................................... 287
Synchronous Transmission (Through TXEN) .......... 288
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Tied to V
Timer0 and Timer1 External Clock .......................... 408
Transition for Entry to Idle Mode ................................ 48
Transition for Entry to SEC_RUN Mode .................... 45
Transition for Entry to Sleep Mode ............................ 47
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
Transition for Wake From Idle to Run Mode .............. 48
Transition for Wake From Sleep (HSPLL) ................. 47
Transition From RC_RUN Mode to PRI_RUN Mode . 46
Transition From SEC_RUN Mode to PRI_RUN Mode
Transition to RC_RUN Mode ..................................... 46
Write, 16-Bit Muliplexed Data, Fully Multiplexed 16-Bit
2
2
2
2
C Slave Mode (7-Bit Reception, SEN = 1) ............ 250
C Slave Mode (7-Bit Transmission) ....................... 244
C Slave Mode General Call Address Sequence (7 or
C Stop Condition Receive or Transmit Mode ........ 263
10-Bit Addressing Mode) ................................. 252
abled) ............................................................... 219
abled) ............................................................... 219
Address ............................................................ 174
dress ................................................................ 173
Strobe .............................................................. 171
plexed Address ................................................ 170
(OST) and Power-up Timer (PWRT) ................ 407
V
V
V
326
(HSPLL) ............................................................. 45
............................................................................ 55
DD
DD
DD
2
2
C Bus Data ................................................. 419
C Bus Start/Stop Bits ................................. 419
), Case 1 ...................................................... 54
), Case 2 ...................................................... 55
Rise < T
PWRT
) ............................................ 54
DD
, V
DD
Rise > T
PWRT
DD
)
,
Timing Diagrams and Specifications
TSTFSZ ........................................................................... 371
Two-Speed Start-up ................................................. 315, 326
Two-Word Instructions
TXSTAx Register
V
V
Voltage Reference Specifications .................................... 399
Voltage Regulator (On-Chip) ........................................... 325
W
Watchdog Timer (WDT) ........................................... 315, 323
WCOL ...................................................... 257, 258, 259, 262
WCOL Status Flag ................................... 257, 258, 259, 262
WWW Address ................................................................ 433
WWW, On-Line Support ...................................................... 7
DDCORE
Write, 16-Bit Muliplexed Data, Partially Multiplexed Ad-
Write, 8-Bit Data, Demultiplexed Address ............... 172
Write, 8-Bit Data, Fully Multiplexed 16-Bit Address . 172
Write, 8-Bit Data, Partially Multiplexed Address ...... 170
Write, 8-Bit Data, Partially Multiplexed Address, Enable
Write, 8-Bit Data, Wait States Enabled, Partially Multi-
Capture/Compare/PWM Requirements (Including ECCP
CLKO and I/O Requirements ........................... 404, 405
EUSART Synchronous Receive Requirements ....... 421
EUSART Synchronous Transmission Requirements ....
Example SPI Mode Requirements (Master Mode, CKE =
Example SPI Mode Requirements (Master Mode, CKE =
Example SPI Mode Requirements (Slave Mode, CKE =
Example SPI Slave Mode Requirements (CKE = 1) 416
External Clock Requirements .................................. 402
I
I
Internal RC Accuracy (INTOSC, INTRC Sources) ... 403
MSSP I
MSSP I
Parallel Master Port Read Requirements ................ 410
Parallel Master Port Write ........................................ 411
Parallel Slave Port Requirements ............................ 409
PLL Clock ................................................................ 403
Program Memory Write Requirements .................... 406
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Timer0 and Timer1 External Clock Requirements ... 408
Example Cases .......................................................... 71
BRGH Bit ................................................................. 275
Operation in Sleep Mode ......................................... 326
Power-up Requirements .......................................... 326
Associated Registers ............................................... 324
Control Register ....................................................... 323
During Oscillator Failure .......................................... 327
Programming Considerations .................................. 323
2
2
C Bus Data Requirements (Slave Mode) .............. 418
C Bus Start/Stop Bits Requirements (Slave Mode) .....
/V
Address ........................................................... 174
dress ................................................................ 173
Strobe .............................................................. 171
plexed Address ................................................ 170
Modules) .......................................................... 412
421
0) ..................................................................... 413
1) ..................................................................... 414
0) ..................................................................... 415
417
(OST), Power-up Timer (PWRT) and Brown-out
Reset ............................................................... 407
CAP
2
2
C Bus Data Requirements ......................... 420
C Bus Start/Stop Bits Requirements .......... 419
Pin .......................................................... 325
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