DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet

IC DSPIC MCU/DSP 24K 18DIP

DSPIC30F3012-30I/P

Manufacturer Part Number
DSPIC30F3012-30I/P
Description
IC DSPIC MCU/DSP 24K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F3012-30IP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
Microchip Technology
Quantity:
1 936
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
TI
Quantity:
6
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F3012-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
The dsPIC30F3012/3013 (Rev. B1) samples that you
have received were found to conform to the
specifications and functionality described in the
following documents:
• DS70157 – “dsPIC30F/33F Programmer’s
• DS70139 – “dsPIC30F2011/2012/3012/3013 Data
• DS70046 – “dsPIC30F Family Reference Manual”
The exceptions to the specifications in the documents
listed above are described in this section. These
exceptions are described for the specific devices that
are listed below:
• dsPIC30F3012
• dsPIC30F3013
These devices may be identified by the following
message that appears in the MPLAB
Window under MPLAB IDE, when a “Reset and
Connect” operation is performed within MPLAB IDE:
Setting Vdd source to target
Target Device dsPIC30F3013 found,
revision = Rev 0x1041
...Reading ICD Product ID
Running ICD Self Test
...Passed
MPLAB ICD 2 Ready
The errata described in this section will be addressed
in
dsPIC30F3013 devices.
© 2008 Microchip Technology Inc.
Reference Manual”
Sheet”
future
revisions
dsPIC30F3012/3013 Rev. B1 Silicon Errata
of
dsPIC30F3012
®
ICD 2 Output
and
dsPIC30F3012/3013
Silicon Errata Summary
The following list summarizes the errata described in
further detail throughout the remainder of this
document:
1.
2.
3.
4.
5.
6.
7.
8.
9.
MAC Class Instructions with ±4 Address
Modification
Sequential MAC instructions, which prefetch data
from Y data space using ±4 address modification
will cause an address error trap.
Decimal Adjust Instruction
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>).
PSV Operations Using SR
In certain instructions, fetching one of the
operands from program memory using Program
Space Visibility (PSV) will corrupt specific bits in
the STATUS Register, SR.
Early Termination of Nested DO Loops
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT (CORCON<11>) bit will produce unexpected
results.
Sequential Interrupts
Sequential interrupts after modifying the CPU IPL,
interrupt IPL, interrupt enable or interrupt flag may
cause an address error trap.
DISI Instruction
The DISI instruction will not disable interrupts if a
DISI instruction is executed in the same
instruction
decrements to zero.
Output Compare Module in PWM Mode
Output compare will produce a glitch when
loading 0% duty cycle in PWM mode. It will also
miss the next compare after the glitch.
Output Compare
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
INT0, ADC and Sleep Mode
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero.
cycle
that
the
DS80255F-page 1
DISI
counter

Related parts for DSPIC30F3012-30I/P

DSPIC30F3012-30I/P Summary of contents

Page 1

... Rev. B1 Silicon Errata The dsPIC30F3012/3013 (Rev. B1) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70139 – “dsPIC30F2011/2012/3012/3013 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” ...

Page 2

... PLL Mode PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. 11. Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet ...

Page 3

... MAC class instructions not use the + = address modification not prefetch data from Y data space. © 2008 Microchip Technology Inc. dsPIC30F3012/3013 2. Module: CPU – Instruction DAW.b The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed ...

Page 4

... Table 1. Example 3 demonstrates the work around for Example 2. DS80255F-page 4 These instructions are identified in Table 1. Example 2 demonstrates one scenario in which this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F3012/3013 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 ...

Page 5

... X; \ DISICNT = 0; } DISI_PROTECT(SRbits.IPL = 0x5); © 2008 Microchip Technology Inc. dsPIC30F3012/3013 5. Module: Interrupt Controller – Sequential Interrupts When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap. The generic terms “Interrupt 1” and “Interrupt 2” are used to represent any two enabled dsPIC30F interrupts ...

Page 6

... Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts for cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from The counter is loaded with 7 at the end of the DISI instruction. ...

Page 7

... GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 8 demonstrates the described above would apply to a dsPIC30F3012 device. DS80255F-page 7 would be or work around ...

Page 8

... EXAMPLE 8: ; ---------------------------------------------------------------------------------------------- .global __reset .global _main .global _GotoSleep .global __AddressError .global __INT1Interrupt ; ---------------------------------------------------------------------------------------------- .section *, code _main: BSET INTCON2, #INT1EP ; Set up INT pins to detect falling edge BCLR IFS1, #INT1IF ; Clear interrupt pin interrupt flag bits BSET IEC1, #INT1IE ; Enable ISR processing for INT pins ...

Page 9

... Clear the I C receiver interrupt flag SI2CF back to step 1 to continue receiving incoming data bytes. © 2008 Microchip Technology Inc. dsPIC30F3012/3013 Work around 2: Use this work around for applications in which the receiver interrupt is required. Assuming that the RBF and the I2COV flags in the I2CSTAT ...

Page 10

... Module: I/O Port – Port Pin Multiplexed with IC1 If the user application enables the auto-baud feature in the UART module, the I/O pin multiplexed with the IC1 (Input Capture) pin cannot be used as a digital input. Work around None. 2 14. Module there are two I ...

Page 11

... For example, if the SDA and SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. © 2008 Microchip Technology Inc. dsPIC30F3012/3013 2 C module is that have 2 ...

Page 12

... APPENDIX A: REVISION HISTORY Revision A (12/2005) Original version of the document. Revision B (9/2006) Added errata and 11. Revision C (9/2007) Added silicon issue 12 (Sleep Mode). Revision D (12/2007) Updated silicon issue 3 (PSV Operations Using SR) 2 and added silicon issues 13 and 14 (I Port – Port Pin Multiplexed with IC1). ...

Page 13

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 14

... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...

Related keywords