PIC24HJ32GP302-I/SO Microchip Technology, PIC24HJ32GP302-I/SO Datasheet
PIC24HJ32GP302-I/SO
Specifications of PIC24HJ32GP302-I/SO
Related parts for PIC24HJ32GP302-I/SO
PIC24HJ32GP302-I/SO Summary of contents
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... PIC24HJ64GPX02/X04 and © 2009 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ128GPX02/X04 High-Performance, 16-bit Microcontrollers Preliminary Data Sheet DS70293D ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash program memory (up to 128 Kbytes) • Data SRAM ( Kbytes) • Boot, Secure and General Security for program Flash © 2009 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Timers/Capture/Compare/PWM: • Timer/Counters five 16-bit timers: - Can pair up to make two 32-bit timers - One timer runs as a Real-Time Clock with an external 32 ...
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... Fully static design • 3.3V (±10%) operating voltage • Industrial and Extended temperature • Low power consumption Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin TQFP/QFN Note: See the device variant tables for exact peripheral features per device. Preliminary © 2009 Microchip Technology Inc. ...
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... PIC24HJ32GP302 Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except PIC24HJ32GP302/304, which include 1 Kbyte of DMA RAM. 2: Only four out of five timers are remappable. 3: Only two out of three interrupts are remappable. © 2009 Microchip Technology Inc. Remappable Peripheral ...
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... OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3 Note 1: The RPx pins can be used by any remappable peripheral. See the table “PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V ...
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... SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See the table “PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © ...
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... AN8/CV /RP18 /PMA2/CN10/RC2 REF OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See the table “PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. DS70293D-page 8 AN11/RP13 AN12/RP12 25 9 PGEC2/RP11 PIC24HJ32GP304 26 8 ...
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... Table of Contents PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Product Families ........................................................ 5 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 15 3.0 CPU............................................................................................................................................................................................ 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory.............................................................................................................................................................. 53 6.0 Resets ....................................................................................................................................................................................... 59 7.0 Interrupt Controller ..................................................................................................................................................................... 67 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 107 9.0 Oscillator Configuration ............................................................................................................................................................ 119 10 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS70293D-page 10 Preliminary © 2009 Microchip Technology Inc. ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices. Figure 1-1 shows a general block diagram of the core and peripheral modules PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2009 Microchip Technology Inc. and families ...
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... FIGURE 1-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks Power-up ...
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... SS2 I/O ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2009 Microchip Technology Inc. PPS Description Analog input channels. No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for peripheral logic and I/O pins. No CPU logic filter capacitor connection. No Ground reference for logic and I/O pins. No Analog voltage reference (high) input. No Analog voltage reference (low) input. Analog = Analog input O = Output TTL = TTL input buffer Preliminary P = Power I = Input © 2009 Microchip Technology Inc. ...
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... Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family of 16-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • ...
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... Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2-2, it EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC24H recommended. A suggested and V specifications are met 470 will limit any current flowing into and V specifications are met. IL © 2009 Microchip Technology Inc. is ...
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... REAL ICE™ In-Circuit Debugger User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. 2.6 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “ ...
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... DS70293D-page 18 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor to V unused pins and drive the output to logic low. Preliminary © 2009 Microchip Technology Inc ...
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... As a result, three parameter instructions can be supported, allowing operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model for the PIC24HJ32GP302/ 304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/ X04 is shown in Figure 3-2. 3.2 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU) ...
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... The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign possible. FIGURE 3-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 ...
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... FIGURE 3-2: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2009 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM ...
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... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70293D-page 22 U-0 U-0 — — (2) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...
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... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...
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... ALU can be written to the W register array or a data memory location. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 CPU hardware support for both multiplication and division. ...
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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is shown in Figure 4-1. PIC24HJ64GPX02/X04 GOTO Instruction Reset Address ...
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... PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs) ...
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... The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. ...
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... DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJ32GP302/304 DEVICES WITH 4 KB RAM Address 2 Kbyte SFR Space 4 Kbyte ...
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... SFR Space 0x07FF 0x0801 8 Kbyte SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2009 Microchip Technology Inc. LSb 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 ...
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... TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 CN30IE CN29IE — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-7: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...
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TABLE 4-10: UART2 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U2MODE 0230 UARTEN — USIDL IREN U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — U2TXREG 0234 — — — — U2RXREG 0236 — — — ...
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... TABLE 4-13: ADC1 REGISTER MAP FOR PIC24HJ64GP202/502, PIC24HJ128GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...
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TABLE 4-15: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...
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TABLE 4-15: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...
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TABLE 4-16: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — ...
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TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 ...
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TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C C1RXF11EID 046E C1RXF12SID 0470 C1RXF12EID 0472 C1RXF13SID 0474 C1RXF13EID 0476 C1RXF14SID 0478 C1RXF14EID ...
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... TABLE 4-20: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...
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... TABLE 4-22: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR PIC24HPIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PMMODE 0602 BUSY IRQM<1:0> PMADDR ADDR15 CS1 0604 PMDOUT1 PMDOUT2 0606 PMDIN1 0608 PMPDIN2 060A PMAEN 060C — ...
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... C2EVT C1EVT CVRCON 0632 — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-27: PORTA REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — ...
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TABLE 4-28: PORTA REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA ...
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... Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register is not present in devices with 32K Flash (PIC24HJ32GP302/304). TABLE 4-33: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ...
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... SOFTWARE STACK In addition to its use as a working register, the W15 register in the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-5 ...
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... The contents of Wn forms the Effective Address (EA). The contents of Wn forms the EA post-modified (incremented or decremented constant value pre-modified (incremented or decremented signed constant value to form the EA. The sum of Wn and Wb forms the EA. The sum of Wn and a literal forms the EA. Preliminary © 2009 Microchip Technology Inc. ...
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... Aside from normal execution, PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • ...
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... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70293D-page 50 Program Counter 0 23 bits TBLPAG 1/0 8 bits 24 bits Select 1 PSVPAG 0 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2009 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2009 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2009 Microchip Technology Inc. ...
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... Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire V range ...
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... RTSP Operation The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time. Table 28-12 shows typical erase and programming times ...
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... Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70293D-page 56 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2009 Microchip Technology Inc. ...
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... RESETS Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 8. “Reset” (DS70229) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
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... SWDTEN bit setting. DS70293D-page 60 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2009 Microchip Technology Inc. (1) (CONTINUED) Preliminary ...
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... System Reset The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR Brown-out Reset (BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source. ...
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... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T © 2009 Microchip Technology Inc. Vbor V BOR ...
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... Power-up timer (PWRT) is too low DD ) for proper device operation. The BOR cir- crosses V DD has elapsed. The delay BOR ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V BOR PWRT trip point BOR © 2009 Microchip Technology Inc. BOR DD ...
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... Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will com- mence. © 2009 Microchip Technology Inc BOR PWRT ...
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... W register access or Security Reset Configuration Mismatch MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Preliminary Cleared by: POR,BOR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR — — © 2009 Microchip Technology Inc. ...
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... IVT. 7.2 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 registers in response to a Reset, which forces the PC to zero. The microcontroller then begins program execution at location 0x000000 ...
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... FIGURE 7-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 ...
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... Microchip Technology Inc. AIVT Address 0x000104 Reserved 0x000106 Oscillator Failure 0x000108 Address Error 0x00010A Stack Error 0x00010C Math Error 0x00010E DMA Error 0x000110 Reserved 0x000112 Reserved 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – ...
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... DMA6 – DMA Channel 6 0x00019E DMA7 – DMA Channel 7 0x0001A0 C1TX – ECAN1 TX Data Request 0x0001A2 Reserved 0x0001A4 Reserved 0x0001A6 Reserved 0x0001A8 Reserved 0x0001AA Reserved 0x0001AC Reserved 0x0001AE Reserved 0x0001B0 Reserved 0x0001B2 Reserved 0x0001B4-0x0001FE Reserved Preliminary Interrupt Source © 2009 Microchip Technology Inc. ...
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... Interrupt Control and Status Registers PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices implement a total of 30 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
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... The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15> DS70293D-page 72 (1) U-0 U-0 — — (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...
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... CPU interrupt priority level is greater than CPU interrupt priority level less Note 1: For complete register details, see Register 3-2: “CORCON: CORE Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2009 Microchip Technology Inc. (1) U-0 U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS70293D-page 74 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request has not occurred DS70293D-page 76 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA0IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. Preliminary DS70293D-page 77 ...
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... Interrupt request has not occurred DS70293D-page 78 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF CMIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC3IF DMA2IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. Preliminary DS70293D-page 79 ...
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... U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) (1) DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 81
... Interrupt request has not occurred bit 13 DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 82
... Note 1: Interrupts disabled on devices without ECAN™ modules. DS70293D-page 82 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DMA6IF CRCIF U2EIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 U1EIF — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 83
... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 ...
Page 84
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70293D-page 84 Preliminary © 2009 Microchip Technology Inc. ...
Page 85
... INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 ...
Page 86
... Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70293D-page 86 Preliminary © 2009 Microchip Technology Inc. ...
Page 87
... Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: Interrupts disabled on devices without ECAN™ modules © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 88
... Unimplemented: Read as ‘0’ DS70293D-page 88 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 89
... Interrupt request not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts disabled on devices without ECAN™ modules. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 90
... Interrupt is priority 1 000 = Interrupt source is disabled DS70293D-page 90 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 92
... Interrupt is priority 1 000 = Interrupt source is disabled DS70293D-page 92 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...
Page 94
... Interrupt is priority 1 000 = Interrupt source is disabled DS70293D-page 94 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CMIP<2:0> bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
Page 96
... Interrupt is priority 1 000 = Interrupt source is disabled DS70293D-page 96 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 97
... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 98
... Note 1: Interrupts disabled on devices without ECAN™ modules. DS70293D-page 98 R/W-0 U-0 R/W-1 (1) — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown (1) © 2009 Microchip Technology Inc. ...
Page 99
... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
Page 100
... Unimplemented: Read as ‘0’ DS70293D-page 100 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 DMA4IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 101
... DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...
Page 102
... Unimplemented: Read as ‘0’ DS70293D-page 102 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2EIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 103
... DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Interrupts disabled on devices without ECAN™ modules. © 2009 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...
Page 104
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70293D-page 104 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 105
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 106
... NOTES: DS70293D-page 106 Preliminary © 2009 Microchip Technology Inc. ...
Page 107
... CPU. To exploit the DMA capability, the corresponding user buffers or variables must be located in DMA RAM. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 peripherals that can utilize DMA are listed in Table 8-1. DMAxPAD Register DMAxREQ Register Values to Read from IRQSEL< ...
Page 108
... Alternatively, an interrupt can be generated when half of the block has been filled. Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus Preliminary DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2009 Microchip Technology Inc. ...
Page 109
... DMACS1, are common to all DMAC channels. DMACS0 contains the DMA RAM and SFR write collision flags, XWCOLx and PWCOLx, respectively. DMACS1 indicates DMA channel and Ping-Pong mode status. © 2009 Microchip Technology Inc. The DMAxCON, DMAxREQ, DMAxCNT are all conventional read/write registers. ...
Page 110
... Continuous, Ping-Pong modes disabled DS70293D-page 110 R/W-0 R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 R/W-0 — MODE<1:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 111
... DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 112
... Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 113
... CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> ...
Page 114
... R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 C = Clear only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 115
... No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2009 Microchip Technology Inc. Preliminary DS70293D-page 115 ...
Page 116
... DMA0STA register selected DS70293D-page 116 U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 117
... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2009 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...
Page 118
... NOTES: DS70293D-page 118 Preliminary © 2009 Microchip Technology Inc. ...
Page 119
... Some registers and associated bits described in this section may not be avail- able on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 9-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSC1 POSCCLK (2) R ...
Page 120
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F peripheral clock time base (F operating speed of the device, and speeds MHz are supported by the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture. Instruction execution speed or device operating frequency, F ...
Page 121
... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. FIGURE 9-2: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2009 Microchip Technology Inc. ...
Page 122
... DS70293D-page 122 Oscillator Source POSCMD<1:0> Internal xx Internal xx Internal xx ) Secondary xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx Preliminary FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 — 011 — 011 1 011 — 010 — 010 1 010 1 001 1 000 © 2009 Microchip Technology Inc. ...
Page 123
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. (1) R-0 ...
Page 124
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70293D-page 124 (1) (CONTINUED) Preliminary © 2009 Microchip Technology Inc. ...
Page 125
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2009 Microchip Technology Inc. R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...
Page 126
... DS70293D-page 126 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 128
... LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD< ...
Page 129
... PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices have two special and power-saving modes that are entered through the families of execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution ...
Page 130
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable mod- ule operation). Preliminary There are eight possible © 2009 Microchip Technology Inc. ...
Page 131
... Unimplemented: Read as ‘0’ bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — R/W-0 R/W-0 ...
Page 132
... DS70293D-page 132 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — OC4MD OC3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 133
... CRCMD: CRC Module Disable bit 1 = CRC module is disabled 0 = CRC module is enabled bit 6 DAC1MD: DAC1 Module Disable bit 1 = DAC1 module is disabled 0 = DAC1 module is enabled bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 R/W-0 — — CMPMD U-0 U-0 U-0 — ...
Page 134
... NOTES: DS70293D-page 134 Preliminary © 2009 Microchip Technology Inc. ...
Page 135
... I/O PORTS Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 10. (DS70230) of the “dsPIC33F/PIC24H Family Reference Manual”, which is avail- able from ...
Page 136
... NOP, as shown in Example 11-1. 11.5 Input Change Notification The input change notification function of the I/O ports allows the PIC24HJ32GP302/304, PIC24HJ64GPX02/ X04 and PIC24HJ128GPX02/X04 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled ...
Page 137
... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2009 Microchip Technology Inc. 11.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it is mapped to ...
Page 138
... RPINR20 SS1 RPINR21 SDI2 RPINR22 SCK2 RPINR22 SS2 RPINR23 CIRX RPINR26 Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> T4CKR<4:0> T5CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> U2RXR<4:0> U2CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0> CIRXR<4:0> © 2009 Microchip Technology Inc. ...
Page 139
... SCK1 SS1 SDO2 SCK2 SS2 C1TX OC1 OC2 OC3 OC4 © 2009 Microchip Technology Inc. FIGURE 11-3: U1TX Output enable U1RTS Output enable 4 OC4 Output U1TX Output U1RTS Output 4 OC4 Output RPn tied to default port pin 00000 RPn tied to Comparator1 Output ...
Page 140
... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. Preliminary © 2009 Microchip Technology Inc. ...
Page 141
... Peripheral Pin Select Registers The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family implement 27 registers for remappable peripheral configuration: • 14 Input Remappable Peripheral Registers: - RPINR0-RPINR1, RPINR3-RPINR4, RPINR7, RPINR10-RPINR11, RPINR18- RPINR23 and PRINR26 • 13 Output Remappable Peripheral Registers: - RPOR0-RPOR12 Note: Input and Output Register values can only ...
Page 142
... Input tied to RP0 DS70293D-page 142 U-0 U-0 — — R/W-1 R/W-1 INT2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 143
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ...
Page 144
... Input tied to RP1 00000 = Input tied to RP0 DS70293D-page 144 R/W-1 R/W-1 T5CKR<4:0> R/W-1 R/W-1 T4CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 145
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 146
... Input tied to RP1 00000 = Input tied to RP0 DS70293D-page 146 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 147
... OCFAR<4:0>: Assign Output Compare A (OCFA) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as ‘0’ ...
Page 148
... Input tied to RP1 00000 = Input tied to RP0 DS70293D-page 148 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 149
... U2RXR<4:0>: Assign UART2 Receive (U2RX) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 U2CTSR<4:0> R/W-1 R/W-1 U2RXR<4:0> Unimplemented bit, read as ‘0’ ...
Page 150
... Input tied to RP1 00000 = Input tied to RP0 DS70293D-page 150 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 151
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 SS1R<4:0> ...
Page 152
... Input tied to RP1 00000 = Input tied to RP0 DS70293D-page 152 R/W-1 R/W-1 SCK2R<4:0> R/W-1 R/W-1 SDI2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 Note 1: This register is disabled on devices without ECAN™ modules. © 2009 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 SS2R<4:0> Unimplemented bit, read as ‘0’ ...
Page 154
... Bit is cleared R/W-0 R/W-0 R/W-0 RP3R<4:0> R/W-0 R/W-0 R/W-0 RP2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 155
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 11-2 for peripheral function numbers) © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R< ...
Page 156
... Bit is cleared R/W-0 R/W-0 R/W-0 RP11R<4:0> R/W-0 R/W-0 R/W-0 RP10R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 157
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 11-2 for peripheral function numbers) © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R< ...
Page 158
... Bit is cleared R/W-0 R/W-0 R/W-0 RP19R<4:0> R/W-0 R/W-0 R/W-0 RP18R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 159
... Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP21R<4:0> R/W-0 ...
Page 160
... Note 1: This register is implemented in 44-pin devices only. DS70293D-page 160 R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 161
... TIMER1 Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70244) of the “dsPIC33F/PIC24H Family Reference Manual”, which is avail- able from the Microchip (www ...
Page 162
... DS70293D-page 162 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 163
... TIMER2/3 AND TIMER4/5 FEATURE Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70244) of the “dsPIC33F/PIC24H Family Reference Manual”, which is avail- ...
Page 164
... The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. Preliminary 32-BIT TIMER TYPE C Timer (msw) Timer3 Timer5 © 2009 Microchip Technology Inc. ...
Page 165
... F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers. 2: Timer Type B Timer ( and 4). 3: Timer Type C Timer ( and 5). © 2009 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw TMRx TMRy 00 x1 TMRyHLD ...
Page 166
... DS70293D-page 166 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 167
... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits have no effect. © 2009 Microchip Technology Inc. U-0 U-0 (1) — ...
Page 168
... NOTES: DS70293D-page 168 Preliminary © 2009 Microchip Technology Inc. ...
Page 169
... The input capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices support up to four input capture channels. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin ...
Page 170
... DS70293D-page 170 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE HC = Cleared in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 171
... OUTPUT COMPARE Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Output Compare” (DS70247) of the “dsPIC33F/ PIC24H Family Reference which is available from the Microchip website (www ...
Page 172
... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match Preliminary — © 2009 Microchip Technology Inc. ...
Page 173
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 174
... NOTES: DS70293D-page 174 Preliminary © 2009 Microchip Technology Inc. ...
Page 175
... SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, Section 18. “Serial Peripheral Interface (SPI)” (DS70243), which is available from the Microchip website (www ...
Page 176
... DS70293D-page 176 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 177
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ...
Page 178
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70293D-page 178 (2) (2) Preliminary © 2009 Microchip Technology Inc. ...
Page 179
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 180
... NOTES: DS70293D-page 180 Preliminary © 2009 Microchip Technology Inc. ...
Page 181
... INTER-INTEGRATED 2 CIRCUIT™ (I C™) Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 19. “Inter-Integrated 2 Circuit™ (I C™)” (DS70235) of the “ ...
Page 182
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...
Page 183
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 184
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70293D-page 184 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master) Preliminary 2 C master) © 2009 Microchip Technology Inc. ...
Page 185
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. U-0 U-0 — — R/C-0 HSC ...
Page 186
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70293D-page 186 2 C slave device address byte. Preliminary © 2009 Microchip Technology Inc. ...
Page 187
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 188
... NOTES: DS70293D-page 188 Preliminary © 2009 Microchip Technology Inc. ...
Page 189
... The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and ® ...
Page 190
... DS70293D-page 190 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 — UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 191
... Note 1: Refer to Section 17. “UART” (DS70232) in the “dsPIC33F/PIC24H Family Reference Manual” for infor- mation on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. MODE REGISTER (CONTINUED) x ...
Page 192
... R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Clear only bit x = Bit is unknown © 2009 Microchip Technology Inc. ...
Page 193
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70232) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary ...
Page 194
... NOTES: DS70293D-page 194 Preliminary © 2009 Microchip Technology Inc. ...
Page 195
... CAN modules or microcontroller devices. This interface/ protocol was designed to allow communications within noisy environments. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices contain up to two ECAN modules. The ECAN module is a communication controller implementing the CAN 2.0 A/B protocol, as defined in the BOSCH CAN specification. The module supports CAN 1 ...
Page 196
... RxF10 Filter RxF9 Filter RxF8 Filter RxF7 Filter RxF6 Filter RxF5 Filter RxF4 Filter RxF3 Filter RxF2 Filter RxF1 Filter RxF0 Filter Buffer Preliminary RxM2 Mask RxM1 Mask RxM0 Mask Control CPU Configuration Bus Logic Interrupts © 2009 Microchip Technology Inc. ...
Page 197
... The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. © 2009 Microchip Technology Inc. Note: Typically, if the ECAN module is allowed to transmit in a particular mode of operation ...
Page 198
... Use buffer window DS70293D-page 198 R/W-0 r-0 R/W-1 ABAT — U-0 R/W-0 U-0 — CANCAP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 REQOP<2:0> bit 8 U-0 R/W-0 — WIN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 199
... DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> • • • 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R-0 ...
Page 200
... TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70293D-page 200 R-0 R-0 R-0 FILHIT<4:0> R-0 R-0 R-0 ICODE<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...