DSPIC30F3013-20I/SO Microchip Technology, DSPIC30F3013-20I/SO Datasheet - Page 65
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DSPIC30F3013-20I/SO
Manufacturer Part Number
DSPIC30F3013-20I/SO
Description
IC DSPIC MCU/DSP 24K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(210 pages)
2.DSPIC30F2011-20ISO.pdf
(6 pages)
3.DSPIC30F3012-20ISO.pdf
(14 pages)
4.DSPIC30F3012-20ISO.pdf
(20 pages)
5.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F3013-20I/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301320ISO
8.0
The dsPIC30F sensor family has up to 21 interrupt
sources and 4 processor exceptions (traps) which must
be arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt Vector
Table (IVT) and transferring the address contained in
the interrupt vector to the program counter. The
interrupt vector is transferred from the program data
bus into the program counter via a 24-bit wide
multiplexer on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in
The
pre-processing
exceptions before they are presented to the processor
core. The peripheral interrupts and traps are enabled,
prioritized and controlled using centralized Special
Function Registers (SFRs):
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
• IPC0<15:0> through IPC10<7:0>
• IPL<3:0>
© 2010 Microchip Technology Inc.
Note:
All interrupt request flags are maintained in these
three registers. The flags are set by their
respective peripherals or external signals and
they are cleared via software.
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
The user assignable priority level associated with
each of these 41 interrupts is held centrally in
these eleven registers.
The current CPU priority level is explicitly stored
in the IPL bits. IPL<3> is present in the CORCON
register, whereas IPL<2:0> are present in the
STATUS register (SR) in the processor core.
interrupt
INTERRUPTS
Figure
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
8-1.
the
controller
interrupts
Reference
is
responsible
and
dsPIC30F2011/2012/3012/3013
processor
Manual”
for
• INTCON1<15:0>, INTCON2<15:0>
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, through the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in
the highest and lowest maskable priorities, respec-
tively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented even if the new interrupt is of higher priority
than the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts,
interrupt-on-change, etc. Control of these features
remains within the peripheral module which generates
the interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program
memory that corresponds to the interrupt. There are 63
different vectors within the IVT (refer to
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Table
and in order to preserve robustness, an address error
trap takes place if the PC attempts to fetch any of these
words
execution of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mapping a data space address into vector space, or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO instruction to this vector space also generates an
address error trap.
Global interrupt control functions are derived from
these two registers. INTCON1 contains the
control and status flags for the processor
exceptions. The INTCON2 register controls the
external interrupt request signal behavior and the
use of the alternate vector table.
Note:
Note:
Note:
8-1). These locations contain 24-bit addresses,
during
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
Assigning a priority level of ‘0’ to an
interrupt source is equivalent to disabling
that interrupt.
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
corresponding
normal
Table
8-1. Levels 7 and 1 represent
execution. This
enable
DS70139G-page 65
bit.
Table
prevents
User
8-1).