PIC24FJ64GA104-I/PT Microchip Technology, PIC24FJ64GA104-I/PT Datasheet - Page 234

• Manufacturer Part Number: PIC24FJ64GA104-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GA104-I/PT

• Core Size: 16-Bit
• Program Memory Size: 64KB (22K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, USART
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, LIN, SPI, USART
• Rohs Compliant: Yes
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240020, DM240002, DM240011, DV164033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

modules are related in this application. This example
measurements, select the internal A/D Channel 31,
programmable delay from an edge event input to the module.
PIC24FJ64GA104 FAMILY
24.2
Time measurements on the pulse width can be similarly
performed using the A/D module’s internal capacitor
(C
Figure 24-2 shows the external connections used for
time measurements, and how the CTMU and A/D
also shows both edge events coming from the external
CTEDG pins, but other configurations using internal
edge sources are possible. For the smallest time
CH0Sx <4:0>= 11111. This minimizes any stray capac-
itance that may otherwise be associated with using an
input pin, thus keeping the total capacitance to that of the
A/D Converter itself (4-5 pF). A detailed discussion on
measuring capacitance and time with the CTMU module
is provided in the “PIC24F Family Reference Manual”.
24.3
The CTMU module can also generate an output pulse with
edges that are not synchronous with the device’s system
clock. More specifically, it can generate a pulse with a
FIGURE 24-2:
FIGURE 24-3:
DS39951B-page 232
AD
) and a precision resistor for current calibration.
Measuring Time
Pulse Generation and Delay
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME
MEASUREMENT
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
CTEDG1
C2INB
C
DELAY
CTEDG1
CTEDG2
ANx
R
PR
EDG1
Preliminary
CV
Current Source
PIC24F Device
Comparator
REF
CTMU
C2
EDG2
EDG1
C
When the module is configured for pulse generation
delay by setting the TGEN bit (CTMUCON<12>), the
internal current source is connected to the B input of
Comparator 2. A capacitor (C
the Comparator 2 pin, C2INB, and the comparator volt-
age reference, CV
is then configured for a specific trip point. The module
begins to charge C
detected. When C
point, a pulse is output on CTPLS. The length of the
pulse delay is determined by the value of C
the CV
Figure 24-3 shows the external connections for pulse
generation, as well as the relationship of the different
analog modules required. While CTEDG1 is shown as
the input pulse source, other options are available. A
detailed discussion on pulse generation with the CTMU
module is provided in the “PIC24F Family Reference
Manual”.
AD
PIC24F Device
A/D Converter
Current Source
CTMU
REF
Output Pulse
trip point.
DELAY
REF
DELAY
, is connected to C2INA. CV
CTPLS
© 2009 Microchip Technology Inc.
charges above the CV
when an edge event is
DELAY
) is connected to
DELAY
REF
and
REF
trip