PIC16C63A-20/SP Microchip Technology, PIC16C63A-20/SP Datasheet
PIC16C63A-20/SP
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PIC16C63A-20/SP Summary of contents
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... CMOS Microcontrollers with A/D Converter Devices included in this data sheet: • PIC16C63A • PIC16C73B • PIC16C65B • PIC16C74B PIC16CXX Microcontroller Core Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • ...
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... RB1 RD4/PSP4 37 RB0/INT RD5/PSP5 36 RD6/PSP6 RD7/PSP7 RD7/PSP7 RD6/PSP6 32 RB0/INT RD5/PSP5 31 RB1 RD4/PSP4 30 RB2 RC7/RX/DT 29 RB3 PIC16C63A PIC16C65B 192 192 28 40 — Yes — — SPI/I C, USART SPI/I C, USART Yes Yes Yes Yes 10 11 28-pin SDIP, SOIC, 40-pin PDIP; SSOP, 44-pin PLCC, ...
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... Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 PIC16C63A/65B/73B/74B Device Varieties ................................................................................................................................. 7 3.0 Architectural Overview ................................................................................................................................................................. 9 4.0 Memory Organization ................................................................................................................................................................. 15 5.0 I/O Ports ..................................................................................................................................................................................... 29 6.0 Timer0 Module ........................................................................................................................................................................... 39 7.0 Timer1 Module ........................................................................................................................................................................... 43 8.0 Timer2 Module ........................................................................................................................................................................... 47 9.0 Capture/Compare/PWM Modules .............................................................................................................................................. 49 10.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 55 11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................................ 65 12 ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 4 2000 Microchip Technology Inc. ...
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... The small footprint packages make this micro- controller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C63A/ 65B/73B/74B devices very versatile, even in areas where no microcontroller use has been considered before (e ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 6 2000 Microchip Technology Inc. ...
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... A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C63A/65B/73B/74B Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 8 2000 Microchip Technology Inc. ...
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... PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file ...
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... OSC1/CLKIN OSC2/CLKOUT MCLR Timer0 Timer1 CCP1 CCP2 Note 1: Higher order bits are from the STATUS register. 2: A/D is not available on the PIC16C63A/65B. 3: PSP and Ports D and E are not available on PIC16C63A/73B. DS30605C-page 10 8 Data Bus Program Counter RAM 8 Level Stack (13-bit) File Registers ...
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... Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: A/D module is not available in the PIC16C63A. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B ...
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... PIC16C63A/65B/73B/74B TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION TQFP DIP PLCC Pin Name MQFP Pin# Pin# Pin# OSC1/CLKIN 13 14 OSC2/CLKOUT 14 15 MCLR (5) RA0/AN0 2 3 (5) RA1/AN1 3 4 (5) RA2/AN2 4 5 (5) RA3/AN3 REF RA4/T0CKI 6 7 (5) RA5/SS/AN4 7 8 RB0/INT 33 36 RB1 34 37 RB2 35 38 RB3 36 39 RB4 ...
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... This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 5: A/D is not available on the PIC16C65B. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B I/O/P Buffer Type Type PORTC is a bi-directional I/O port ...
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... PIC16C63A/65B/73B/74B 3.1 Clocking Scheme/Instruction Cycle The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro- gram counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruc- tion is decoded and executed during the following Q1 through Q4 ...
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... MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16C63A/65B/73B/74B has a 13-bit program counter capable of addressing program memory space. All devices covered by this data sheet have bits of program memory. The address range is 0000h - 0FFFh for all devices. Accessing a location above 0FFFh will cause a wrap- around ...
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... Note 1: Not a physical register. 2: These registers are not implemented on the PIC16C63A/73B, read as '0'. 3: These registers are not implemented on the PIC16C63A/65B, read as '0'. DS30605C-page 16 4.2.2 SPECIAL FUNCTION REGISTERS File The Special Function Registers are registers used by ...
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... Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 4: These registers can be addressed from either bank. 5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and registers clear. 6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear. ...
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... Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 4: These registers can be addressed from either bank. 5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and registers clear. 6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear. ...
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... Legend Readable bit -n = Value at POR 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B It is recommended that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS regis- ter. These instructions do not affect the bits in the STATUS register. For other instructions which do not affect status bits, see the " ...
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... PIC16C63A/65B/73B/74B 4.2.2.2 OPTION Register The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the external INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: OPTION_REG REGISTER (ADDRESS 81h) R/W-1 R/W-1 RBPU INTEDG ...
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... Note 1: A mismatch condition will exist until PORTB is read. After reading PORTB, the RBIF flag bit can be cleared. Legend Readable bit -n = Value at POR 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User soft- ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented; always maintain this bit clear. 2: PIC16C63A/65B devices do not have an A/D implemented; always maintain this bit clear. Legend Readable bit -n = Value at POR ...
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... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented. This bit loca- tion is reserved on these devices. 2: PIC16C63A/65B devices do not have an A/D implemented. This bit location is reserved on these devices ...
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... PIC16C63A/65B/73B/74B 4.2.2.6 PIE2 Register This register contains the individual enable bit for the CCP2 peripheral interrupt. REGISTER 4-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 — bit 7 bit 7-1 Unimplemented: Read as '0' bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt ...
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... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit -n = Value at POR 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Note: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a “ ...
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... PIC16C63A/65B/73B/74B 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared ...
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... Data Memory 7Fh Bank 0 Note 1: For register file map detail, see Figure 4-2. 2: Shaded portions are not implemented; maintain the IRP and RP1 bits clear. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B EXAMPLE 4-2: movlw movwf NEXT clrf incf btfss goto ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 28 2000 Microchip Technology Inc. ...
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... MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as ’0’. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B FIGURE 5-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Bus Port CK Q Data Latch ...
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... ADCON1 Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented; maintain this register clear. DS30605C-page 30 Function Digital input/output or analog input. ...
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... PORTB. The “mismatch” outputs of RB7:RB4 are OR’d together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB ...
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... PIC16C63A/65B/73B/74B TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer (1) RB0/INT bit0 TTL/ST RB1 bit1 TTL RB2 bit2 TTL RB3 bit3 TTL RB4 bit4 TTL RB5 bit5 TTL (2) RB6 bit6 TTL/ST (2) RB7 bit7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. ...
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... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h PORTC RC7 RC6 87h TRISC PORTC Data Direction register Legend unknown unchanged 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B FIGURE 5-5: PORT/PERIPHERAL Select Peripheral Data Out Data Bus D WR Port CK Data Latch D WR TRIS CK ...
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... PIC16C63A/65B/73B/74B 5.4 PORTD and TRISD Registers Note: The PIC16C63A and PIC16C73B do not provide PORTD. The PORTD and TRISD registers are not implemented. PORTD is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configured as an input or output. PORTD can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit PSPMODE (TRISE< ...
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... PORTE and TRISE Register Note 1: The PIC16C63A and PIC16C73B do not provide PORTE. The PORTE and TRISE registers are not implemented. 2: The PIC16C63A/65B does not provide an A/D module. A/D functions are not imple- mented. PORTE has three pins: RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configured as inputs or outputs ...
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... PIC16C63A/65B/73B/74B REGISTER 5-1: TRISE REGISTER (ADDRESS 89h) R-0 IBF OBF bit 7 bit 7 IBF: Input Buffer Full Status bit word has been received and is waiting to be read by the CPU word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word ...
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... Parallel Slave Port (PSP) Note: The PIC16C63A and PIC16C73B do not provide a parallel slave port. The PORTD, PORTE, TRISD and TRISE registers are not implemented. PORTD operates as an 8-bit wide Parallel Slave Port (PSP), or microprocessor port when control bit PSP- MODE (TRISE<4>) is set. In Slave mode asyn- ...
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... PIC16C63A/65B/73B/74B FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Address Name Bit 7 Bit 6 Bit 5 08h PORTD Port data latch when written, Port pins when read ...
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... Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment, either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 (OPTION_REG< ...
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... PIC16C63A/65B/73B/74B 6.2 Using Timer0 with an External Clock The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the synchronized input on the Q2 and Q4 cycles of the internal phase clocks. Therefore necessary for T0CKI to be high for at least 2 T (and a small RC delay of 20 ns) and ...
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... TMR0 Timer0 Module’s register 0Bh,8Bh INTCON GIE PEIE 81h OPTION_REG RBPU INTEDG Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 42 2000 Microchip Technology Inc. ...
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... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Timer1 also has an internal “RESET input”. This RESET can be generated by either of the two CCP modules (Section 9 ...
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... PIC16C63A/65B/73B/74B 7.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is F /4. The synchronize control bit T1SYNC OSC (T1CON<2>) has no effect since the internal clock is always in sync. FIGURE 7-1: TIMER1 BLOCK DIAGRAM ...
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... Table 7-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B TABLE 7-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq ...
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... Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. ...
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... Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 8.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • ...
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... Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. ...
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... Capture None. PWM Compare None. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B CCP2 Module: Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled) ...
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... PIC16C63A/65B/73B/74B REGISTER 9-1: CCP1CON REGISTER/CCP2CON REGISTER U-0 — bit 7 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. ...
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... Enable Edge Detect TMR1H CCP1CON<3:0> Q’s 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 9.1.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro- nized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. ...
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... PIC16C63A/65B/73B/74B 9.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON< ...
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... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 9.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON< ...
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... Legend unknown unchanged unimplemented, read as ’0’. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16C63A/73B; always maintain these bits clear. 2: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits clear. TABLE 9-5: ...
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... Slave mode (SCK is the clock input) • Clock Polarity (Idle state of SCK) • Clock edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B FIGURE 10-1: Read RC4/SDI/SDA RC5/SDO Manual SS Control ...
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... PIC16C63A/65B/73B/74B REGISTER 10-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 SMP bit 7 bit 7 SMP: SPI Data Input Sample Phase SPI Master mode Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire SPI Slave mode: ...
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... C Slave mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend Readable bit -n = Value at POR 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 ...
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... PIC16C63A/65B/73B/74B FIGURE 10-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit7 SDO SDI (SMP = 0) bit7 SDI (SMP = 1) bit7 SSPIF FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) ...
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... Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. ...
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... PIC16C63A/65B/73B/74B 2 10.3 SSP I C Operation 2 The SSP module mode fully implements all slave functions, except general call support, and provides interrupts on START and STOP bits in hardware to facilitate firmware implementation of the master func- tions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. ...
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... Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 1. Receive first (high) byte of address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). 2. Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line) ...
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... PIC16C63A/65B/73B/74B 10.3.1.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow con- ...
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... SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>) 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse ...
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... Legend unknown unchanged unimplemented locations read as ’0’. Shaded cells are not used by SSP module in I Note 1: PSPIF and PSPIE are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: ADIF and ADIE are reserved on the PIC16C63A/65B; always maintain these bits clear. ...
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... TX9D: 9th bit of Transmit Data. Can be parity bit. Legend Readable bit -n = Value at POR 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B as a half duplex synchronous system that can commu- nicate with peripheral devices, such as A/D or D/A inte- grated circuits, Serial EEPROMs etc. The USART can be configured in the following modes: • ...
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... PIC16C63A/65B/73B/74B REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins Serial port disabled bit 6 RX9: 9-bit Receive Enable bit ...
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... SPBRG Baud Rate Generator register Legend unknown unimplemented, read as '0'. Shaded cells are not used by the BRG. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the F OSC baud rate error in some cases. ...
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... PIC16C63A/65B/73B/74B 11.2 USART Asynchronous Mode In this mode, the USART uses standard non- return-to-zero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8 bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART trans- mits and receives the LSb first. The USART’ ...
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... Legend unchanged unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. ...
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... PIC16C63A/65B/73B/74B 11.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 11-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate ...
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... Legend unchanged unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 5 ...
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... PIC16C63A/65B/73B/74B 11.2.3 USART SYNCHRONOUS MASTER MODE In Synchronous Master mode, the data is transmitted in a half-duplex manner, i.e., transmission and reception do not occur at the same time. When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively ...
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... Legend unchanged unknown unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. ...
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... PIC16C63A/65B/73B/74B 11.2.5 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the recep- tion is continuous until CREN is cleared ...
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... Legend unchanged unknown unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. ...
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... PIC16C63A/65B/73B/74B 11.3 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA< ...
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... Legend unchanged unknown unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. ...
Page 78
... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 78 2000 Microchip Technology Inc. ...
Page 79
... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE Note: The PIC16C63A and PIC16C65B do not include A/D modules. ADCON0, ADCON1 and ADRES registers are not imple- mented. ADIF and ADIE bits are reserved and should be maintained clear. The 8-bit Analog-to-Digital (A/D) converter module has five inputs for the PIC16C73B and eight for the PIC16C74B ...
Page 80
... PIC16C63A/65B/73B/74B REGISTER 12-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 — bit 7 bit 7-3 Unimplemented: Read as '0' bit 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x A = Analog input Note 1: RE0, RE1 and RE2 are implemented on the PIC16C74B only. ...
Page 81
... A/D Converter V REF (Reference Voltage) Note 1: Not available on PIC16C73B. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 3. Wait the required acquisition time. 4. Set GO/DONE bit (ADCON0) to start conversion. 5. Wait for A/D conversion to complete, by either: Polling for the GO/DONE bit to be cleared (if interrupts are disabled); ...
Page 82
... PIC16C63A/65B/73B/74B 12.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-2. The source impedance (R ) and the internal sampling ...
Page 83
... AD on the selected channel. The GO/DONE bit can then be set to start another conversion. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 12.5 A/D Operation During SLEEP The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC ...
Page 84
... PIC16C63A/65B/73B/74B TABLE 12-1: SUMMARY OF A/D REGISTERS (PIC16C73B/74B ONLY) Address Name Bit 7 Bit 6 INTCON GIE PEIE 0Bh,8Bh (1) PIR1 PSPIF ADIF 0Ch (1) PIE1 PSPIE ADIE 8Ch PIR2 — — 0Dh PIE2 — — 8Dh ADRES A/D Result register 1Eh ADCON0 ADCS1 ADCS0 1Fh ADCON1 — ...
Page 85
... PWRTE. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The ...
Page 86
... PIC16C63A/65B/73B/74B 13.2 Oscillator Configurations 13.2.1 OSCILLATOR TYPES The PIC16CXX can be operated in four different oscil- lator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • ...
Page 87
... ECS ECS-10-13-1 4 MHz ECS ECS-40-20-1 8 MHz EPSON CA-301 8.000M-C 20 MHz EPSON CA-301 20.000M-C 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Note 1: Higher capacitance increases the stability of the oscillator, but also increases the OSC2 start-up time 100 pF 2: Since each resonator/crystal has its own ...
Page 88
... PIC16C63A/65B/73B/74B 13.3 RESET The PIC16CXX differentiates between various kinds of RESET: • Power-on Reset (POR) • MCLR Reset during normal operation • MCLR Reset during SLEEP • WDT Reset (normal operation) • Brown-out Reset (BOR) Some registers are not affected in any RESET condi- tion ...
Page 89
... The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 13.4.4 BROWN-OUT RESET (BOR) The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit ...
Page 90
... PIC16C63A/65B/73B/74B TABLE 13-3: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration PWRTE = 0 XT, HS 1024T TABLE 13-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD Power-on Reset Illegal set on POR Illegal set on POR Brown-out Reset WDT Reset WDT Wake- MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP ...
Page 91
... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 13-5 for RESET value for specific condition. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Power-on Reset MCLR Resets Brown-out Reset WDT Reset ...
Page 92
... PIC16C63A/65B/73B/74B TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADCON0 63A 65B 73B OPTION_REG 63A 65B 73B TRISA 63A 65B 73B TRISB 63A 65B 73B TRISC 63A 65B 73B TRISD 63A 65B 73B TRISE 63A 65B 73B 63A ...
Page 93
... Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or the GIE bit. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Note interrupt occurs while the Global Inter- rupt Enable (GIE) bit is being cleared, the GIE bit may unintentionally be re-enabled by the user’ ...
Page 94
... SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF PIC16C63A Yes Yes Yes PIC16C65B Yes Yes Yes PIC16C73B Yes Yes Yes PIC16C74B Yes Yes Yes 13.5.1 ...
Page 95
... SLEEP mode, a WDT time-out causes the device to wake-up and resume normal operation (Watchdog Timer Wake-up). The WDT can be permanently disabled by clearing configuration bit WDTE (Section 13.1). 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B The example: a) Stores the W register. b) Stores the STATUS register in bank 0. ...
Page 96
... PIC16C63A/65B/73B/74B 13.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions (V = Min., Temperature = Max., and DD max. WDT prescaler), it may take several seconds before a WDT time-out occurs. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed ...
Page 97
... A/D conversion (when A/D clock source is RC). 7. USART (Synchronous Slave mode). 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 98
... PIC16C63A/65B/73B/74B FIGURE 13-7: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 Instruction Inst( Inst(PC) = SLEEP Fetched Instruction SLEEP Inst( Executed Note 1: XT oscillator mode assumed 1024Tosc (drawing not to scale). This delay is not present in RC osc mode. ...
Page 99
... Register bit field In the set of i talics User defined term (font is courier) 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction ...
Page 100
... PIC16C63A/65B/73B/74B TABLE 14-2: PIC16CXX INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
Page 101
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B ANDWF AND W with f Syntax: [label] ANDWF Operands 127 d Operation: (W) .AND. (f) Status Affected: ...
Page 102
... PIC16C63A/65B/73B/74B BTFSS Bit Test f, Skip if Set Syntax: [label] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ’b’ in register ’f’ is ’0’, the next instruction is executed. If bit ’b’ is ’1’, then the next instruction ...
Page 103
... If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead making instruction. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B GOTO Unconditional Branch Syntax: [ label ] Operands ...
Page 104
... PIC16C63A/65B/73B/74B IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k Operands 255 Operation: (W) .OR. k (W) Status Affected: Z Description: The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register. IORWF Inclusive OR W with f Syntax: [ label ] IORWF Operands 127 ...
Page 105
... TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B RLF Rotate Left f through Carry Syntax: [ label ] Operands 127 d [0,1] ...
Page 106
... PIC16C63A/65B/73B/74B SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Operands 255 Operation (W) W) Status Affected: C, DC, Z Description: The W register is subtracted (2’s com- plement method) from the eight bit lit- eral 'k'. The result is placed in the W register. SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d ...
Page 107
... Customizable toolbar and key mapping • A status bar • On-line help 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro emulator and simulator tools (auto- matically updates all project information) • ...
Page 108
... PIC16C63A/65B/73B/74B 15.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for pre- compiled code to be used with the MPLINK object linker ...
Page 109
... PIC16C92X PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 15.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ...
Page 110
... PIC16C63A/65B/73B/74B 15.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple dem- onstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Mod- ule. All the necessary hardware and software is included to run the basic demonstration programs ...
Page 111
... PIC16C6X á á á á PIC16C5X á á á PIC14000 á á á á PIC12CXXX Tools Software Emulators 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B á á á á á á á á á á á á á á á á á á ...
Page 112
... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 112 2000 Microchip Technology Inc. ...
Page 113
... Thus, a series resistor 100 should be used when applying a “low” level to the MCLR/V than pulling this pin directly PORTD and PORTE not available on the PIC16C63A/73B. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device ...
Page 114
... PIC16C63A/65B/73B/74B FIGURE 16-1: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V FIGURE 16-2: PIC16LC63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2 (12.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10MHz. ...
Page 115
... FIGURE 16-3: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B PIC16CXXX-04 4 MHz Frequency DS30605C-page 115 ...
Page 116
... PIC16C63A/65B/73B/74B 16.1 DC Characteristics PIC16LC63A/65B/73B/74B-04 ‡ PIC16C63A/65B/73B/74B-04 ‡ PIC16C6A/65B/73B/74B-20 Param Sym Characteristic No. V Supply Voltage DD PIC16LCXXX D001 PIC16CXXX D001 D001A D002* V RAM Data Retention DR Voltage (Note 1) D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to VDD DD D004A* ensure internal ...
Page 117
... PICmicro device be driven with external clock in RC mode. 9: The leakage current on the MCLR/V els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10: Negative current is defined as current sourced by the pin. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C T -40° ...
Page 118
... PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 ‡ PIC16C63A/65B/73B/74B-04 ‡ PIC16C6A/65B/73B/74B-20 Param Sym Characteristic No. Module Differential Current (Note 6) D022* I Watchdog Timer WDT D022A* I Brown-out Reset BOR Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) ...
Page 119
... PICmicro device be driven with external clock in RC mode. 9: The leakage current on the MCLR/V els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10: Negative current is defined as current sourced by the pin. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C T -40° ...
Page 120
... PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 ‡ PIC16C63A/65B/73B/74B-04 ‡ PIC16C6A/65B/73B/74B-20 Param Sym Characteristic No. Output Low Voltage D080 V I/O ports OL D083 OSC2/CLKOUT (RC osc mode) Output High Voltage D090 V I/O ports (Note 10) OH D092 OSC2/CLKOUT (RC osc mode) D150* V Open-Drain OD High Voltage * These parameters are characterized but not tested. ...
Page 121
... PICmicro device be driven with external clock in RC mode. 9: The leakage current on the MCLR/V els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10: Negative current is defined as current sourced by the pin. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C T -40° ...
Page 122
... PIC16C63A/65B/73B/74B 16.2 AC (Timing) Characteristics 16.2.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: ...
Page 123
... Operating temperature AC CHARACTERISTICS Operating voltage V LC parts operate for commercial/industrial temperatures only. FIGURE 16-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Pin Note 1: PORTD and PORTE are not implemented on the PIC16C63A/73B. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 0°C T +70°C A -40°C T +85° ...
Page 124
... PIC16C63A/65B/73B/74B 16.2.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 16-5: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No External CLKIN Frequency OSC (Note 1) Oscillator Frequency (Note External CLKIN Period OSC (Note 1) Oscillator Period (Note Instruction Cycle Time (Note 1) ...
Page 125
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ††These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC mode where CLKOUT output 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B ...
Page 126
... PIC16C63A/65B/73B/74B FIGURE 16-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset I/O Pins Note: Refer to Figure 16-4 for load conditions. FIGURE 16-8: BROWN-OUT RESET TIMING V DD ...
Page 127
... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B ...
Page 128
... PIC16C63A/65B/73B/74B FIGURE 16-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture mode) CCPx (Compare or PWM mode) Note: Refer to Figure 16-4 for load conditions. TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Sym Characteristic No. 50* TccL CCP1 and No Prescaler CCP2 With Prescaler PIC16CXX ...
Page 129
... TrdH2dtI data out invalid * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 65 Characteristic Min 20 20 ...
Page 130
... PIC16C63A/65B/73B/74B FIGURE 16-12: EXAMPLE SPI MASTER MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) 80 SDO SDI MSb IN 73 Note: Refer to Figure 16-4 for load conditions. TABLE 16-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param Symbol Characteristic No. 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input ...
Page 131
... TdoV2scL † Data in “Typ” column 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 72 80 BIT6 - - - - - -1 LSb 75, 76 ...
Page 132
... PIC16C63A/65B/73B/74B FIGURE 16-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) 80 SDO SDI SDI MSb IN 73 Note: Refer to Figure 16-4 for load conditions. TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0) Param Symbol Characteristic No. ...
Page 133
... TscL2ssH † Data in “Typ” column 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B 72 80 BIT6 - - - - - -1 LSb 75, 76 ...
Page 134
... PIC16C63A/65B/73B/74B 2 FIGURE 16-16 BUS START/STOP BITS TIMING SCL 91 90 SDA START Condition Note: Refer to Figure 16-4 for load conditions. 2 TABLE 16-12 BUS START/STOP BITS REQUIREMENTS Param Sym Characteristic No. 90 START condition SU STA Setup time 91 START condition HD STA Hold time 92 STOP condition ...
Page 135
... LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T 2 dard mode I C bus specification) before the SCL line is released. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Min Max 100 kHz mode 4.0 — ...
Page 136
... PIC16C63A/65B/73B/74B FIGURE 16-18: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 RC7/RX/DT pin 120 Note: Refer to Figure 16-4 for load conditions. TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym No. 120* TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid ...
Page 137
... A/D module current is from the RA3 pin or the V REF 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Min Typ† Max Units — ...
Page 138
... PIC16C63A/65B/73B/74B FIGURE 16-20: A/D CONVERSION TIMING BSF ADCON0, GO 134 (T /2) OSC Q4 132 A/D CLK 7 A/D DATA ADRES ADIF GO SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T instruction to be executed. TABLE 16-17: A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. ...
Page 139
... V range). This is for information only and devices are ensured to operate properly only within the specified range. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B The data presented in this section is a statistical sum- mary of data collected on units from different lots over a period of time. Note: Standard deviation is denoted by sigma ( ). • ...
Page 140
... PIC16C63A/65B/73B/74B FIGURE 17-1: TYPICAL 2 FIGURE 17-2: MAXIMUM 2 DS30605C-page 140 vs. F OVER V – HS MODE OSC DD 5.5 V 5.0 V 4.5 V 4.0 V 3 (MHz) OSC vs. F OVER V – HS MODE OSC DD 5.5 V 5.0 V 4.5 V 4.0 V 3 (MHz) OSC Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – ...
Page 141
... TYPICAL I DD 100 FIGURE 17-4: MAXIMUM I DD 160 140 120 100 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B vs. F OVER V – LP MODE OSC DD 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3 (kHz) OSC vs. F OVER V – LP MODE OSC DD 5.5 V 5.0 V 4.5 V 4.0 V 3 ...
Page 142
... PIC16C63A/65B/73B/74B FIGURE 17-5: TYPICAL I DD 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 FIGURE 17-6: MAXIMUM I DD 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 DS30605C-page 142 vs. F OVER V – XT MODE OSC DD 1.5 2 ...
Page 143
... FIGURE 17-8: AVERAGE F OSC 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B vs. V FOR VARIOUS RESISTANCES – RC MODE Typical: Maximum: mean + 3 (-40°C to 125°C) Minimum: Not recommended for operation over 4 MHz 3.5 4.0 4 ...
Page 144
... PIC16C63A/65B/73B/74B FIGURE 17-9: AVERAGE F OSC 1,000 900 800 700 600 500 400 300 200 100 0 2.5 3.0 FIGURE 17-10: V vs. V OVER TEMPERATURE – TTL INPUT TH DD 2.0 1.8 1.6 1.4 Max (-40°C) 1.2 Typ (25°C) 1.0 Min (125°C) 0.8 0.6 ...
Page 145
... Microchip Technology Inc. PIC16C63A/65B/73B/74B OVER TEMPERATURE – SCHMITT TRIGGER INPUT (I Typical: Maximum: mean + 3 (-40°C to 125°C) Minimum: 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE – SCHMITT TRIGGER INPUT Typical: Maximum: mean + 3 (-40° ...
Page 146
... PIC16C63A/65B/73B/74B FIGURE 17-13 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 FIGURE 17-14 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 DS30605C-page 146 = 3 Typical: Maximum: mean + 3 (-40°C to 125°C) Minimum: Max (-40°C) Typical (25°C) Min (125°C) ...
Page 147
... FIGURE 17-16 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B = 3 Typical: Maximum: mean + 3 (-40°C to 125°C) Minimum: Max (125°C) Typ (25°C) Min (-40° (-mA 5 Typical: Maximum: mean + 3 (-40°C to 125°C) Minimum: Max (125° ...
Page 148
... PIC16C63A/65B/73B/74B FIGURE 17-17: I vs. V (85°C) – SLEEP MODE, ALL PERIPHERALS DISABLED PD DD 140 120 100 2.5 3.0 FIGURE 17-18: I vs. V (125°C) – SLEEP MODE, ALL PERIPHERALS DISABLED PD DD 1,400 1,200 1,000 800 600 400 200 0 2.5 3.0 DS30605C-page 148 Typical: Maximum: mean + 3 (-40° ...
Page 149
... FIGURE 17-20: I vs. V TIMER 1 120 100 2.5 3.0 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B OVER TEMPERATURE (-40°C TO +125°C) Typical: Maximum: mean + 3 (-40°C to 125°C) Minimum: Device Indeterminant SLEEP State Device in RESET 3.5 4.0 V (V) DD (-10°C TO +70°C) ...
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... PIC16C63A/65B/73B/74B FIGURE 17-21: I vs. V WDT 2.5 3.0 FIGURE 17-22: WDT PERIOD vs Maximum (125° Typical (25° Minimum (-40° 2.5 3.0 DS30605C-page 150 (-40°C TO +125°C) Typical: Maximum: mean + 3 (-40°C to 125°C) Minimum: 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE (-40°C TO +125°C) ...
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... FIGURE 17-23: AVERAGE WDT PERIOD vs 2.5 3.0 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B OVER TEMPERATURE (-40°C TO +125°C) DD Typical: Maximum: mean + 3 (-40°C to 125°C) Minimum: 125°C 85°C 25°C -40°C 3.5 4.0 4.5 V (V) DD statistical mean @ 25°C mean – 3 (-40°C to 125°C) 5 ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 152 2000 Microchip Technology Inc. ...
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... Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Example PIC16C73B-04/SP 0017HAT ...
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... PIC16C63A/65B/73B/74B Package Marking Information (Cont’d) 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead CERDIP Windowed XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead MQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30605C-page 154 Example PIC16C74B-04/P ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Units INCHES* MIN NOM MAX ...
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... PIC16C63A/65B/73B/74B 18.3 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Units INCHES* ...
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... PIC16C63A/65B/73B/74B 18.5 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Units INCHES* MIN NOM ...
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... PIC16C63A/65B/73B/74B 18.7 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
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... Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B ...
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... PIC16C63A/65B/73B/74B 18.9 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form (MQFP #leads= Dimension Limits Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff § Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B D D1 CH1 Units ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 164 2000 Microchip Technology Inc. ...
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... PIC16C63A A/D no Parallel Slave Port no Packages 28-pin PDIP, 28-pin windowed CERDIP, 28-pin SOIC, 28-pin SSOP 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Revision Description have been specified graphs for device operating area (in Electrical DD Specifications) TM Mid-Range MCU Family Reference Manual, PIC16C65B PIC16C73B no 5 channels, 8 bits ...
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... This allows conversion of digital inputs. (A/D on PIC16C73X/74X only.) H/W - Issues may exist with regard to the application circuits. S/W - Issues may exist with regard to the user program. Prog. - Issues may exist when writing the program to the controller. DS30605C-page 166 PIC16C63A/65B/73B/74B H/W S/W Prog. 2000 Microchip Technology Inc. ✔ — ...
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... PIC16CXX — PIC16LCXX PIC16CXX — PIC16LCXX PIC16CXX — — 50 PIC16LCXX — — 50 drops below V DD BOR cycle. CY PIC16C63A/65B/73B/74B Unit Min Typ† Max 4.0 — 5.5 V (1) — 5 BOR 3.65 — 4. — 8.5 V 2.5 — 0 — ...
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... PIC16C63A/65B/73B/74B APPENDIX D: MIGRATION FROM BASELINE TO MID-RANGE DEVICES This section discusses how to migrate from a baseline device (i.e., PIC16C5X mid-range device (i.e., PIC16CXXX). The following are the list of modifications over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14-bits. This allows larger page sizes, both in program ...
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... RB7:RB4 Port Pins ..................................................... 31 2 SSP Mode......................................................... 60 SSP in SPI Mode ........................................................ 55 Timer0/WDT Prescaler................................................ 39 Timer2 ......................................................................... 47 USART Receive.......................................................... 70 USART Transmit ......................................................... 68 Watchdog Timer .......................................................... 96 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B BOR bit ......................................................................... 25, 89 BRGH bit ............................................................................ 67 Brown-out Reset (BOR) Timing Diagram ........................................................ 126 Buffer Full Status bit, BF..................................................... bit .................................................................................... 19 Capture/Compare/PWM Capture Block Diagram .................................................... 51 CCP1CON Register ...
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... PIC16C63A/65B/73B/74B D D/A ...................................................................................... 56 Data Memory Register File Map ........................................................ 16 Data/Address bit, D/A.......................................................... 56 DC bit .................................................................................. 19 Development Support ........................................................... 5 Device Differences ............................................................ 165 Direct Addressing................................................................ 27 E Electrical Characteristics................................................... 113 Errata .................................................................................... 3 F FERR bit.............................................................................. 66 FSR Register........................................................... 17, 18 General Description .............................................................. 5 GIE bit ................................................................................. 93 I I/O Ports PORTA ........................................................................ 29 PORTB........................................................................ 31 PORTC........................................................................ 33 PORTD.................................................................. 34, 37 PORTE ...
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... RB5 ....................................................................... 11, 12 RB6 ....................................................................... 11, 12 RB7 ....................................................................... 11, 12 RC0/T1OSO/T1CKI .............................................. 11, 13 RC1/T1OSI/CCP2................................................. 11, 13 RC2/CCP1 ............................................................ 11, 13 RC3/SCK/SCL ...................................................... 11, 13 RC4/SDI/SDA ....................................................... 11, 13 RC5/SDO .............................................................. 11, 13 RC6/TX/CK ............................................... 11, 13, 65–76 RC7/RX/DT ............................................... 11, 13, 65–76 RD0/PSP0................................................................... 13 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B RD1/PSP1 .................................................................. 13 RD2/PSP2 .................................................................. 13 RD3/PSP3 .................................................................. 13 RD4/PSP4 .................................................................. 13 RD5/PSP5 .................................................................. 13 RD6/PSP6 .................................................................. 13 RD7/PSP7 .................................................................. 13 RE0/RD/AN5 .............................................................. 13 RE1/WR/AN6.............................................................. 13 RE2/CS/AN7............................................................... 13 V ........................................................................11, 13 ...
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... PIC16C63A/65B/73B/74B R R/W ..................................................................................... 56 R/W bit .................................................................... 61, 62, 63 RBIF bit ......................................................................... 31, 94 RBPU bit ............................................................................. 20 RC Oscillator ................................................................. 87, 90 RCSTA Register.................................................................. 66 RD pin ................................................................................. 37 Read/Write bit Information, R/W ......................................... 56 Receive Overflow Indicator bit, SSPOV .............................. 57 Register File ........................................................................ 15 Register File Map ................................................................ 16 Registers Maps PIC16C73 ........................................................... 16 PIC16C73A ......................................................... 16 PIC16C74 ........................................................... 16 PIC16C74A ......................................................... 16 RESET Conditions ...................................................... 90 SSPSTAT .................................................................... 56 Summary..................................................................... 17 RESET ...
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... TOUTPS2 bit....................................................................... 47 TOUTPS3 bit....................................................................... 47 TRISA Register ............................................................. 18, 29 TRISB Register ............................................................. 18, 31 TRISC Register ............................................................. 18, 33 TRISD Register ............................................................. 18, 34 TRISE Register ....................................................... 18, 35, 36 TXSTA Register .................................................................. 65 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B U UA....................................................................................... 56 Universal Synchronous Asynchronous Receiver Transmitter (USART) .......................................................... 65 Update Address bit, UA ...................................................... 56 USART Asynchronous Mode................................................... 68 Asynchronous Receiver.............................................. 70 Asynchronous Reception ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 174 2000 Microchip Technology Inc. ...
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... Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16C63A/65B/73B/74B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this data sheet easy to follow? If not, why? 4 ...
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... The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B /XX XXX Examples: Package ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 178 2000 Microchip Technology Inc. ...
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... NOTES: 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B DS30605C-page 179 ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 180 2000 Microchip Technology Inc. ...
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... NOTES: 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B DS30605C-page 181 ...
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... PIC16C63A/65B/73B/74B NOTES: DS30605C-page 182 2000 Microchip Technology Inc. ...
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... NOTES: 2000 Microchip Technology Inc. PIC16C63A/65B/73B/74B DS30605C-page 183 ...
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... Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. ...