PIC16C63A-20/SP Microchip Technology, PIC16C63A-20/SP Datasheet - Page 88

• Manufacturer Part Number: PIC16C63A-20/SP
• Description: IC MCU OTP 4KX14 PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63A-20/SP

• Program Memory Type: OTP
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVMCPA - KIT DVR BOARD EVAL SYSTEM MXDEV1
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16C63A/65B/73B/74B
13.3
The PIC16CXX differentiates between various kinds of
RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR)
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on POR, on the MCLR and WDT Reset,
FIGURE 13-4:
DS30605C-page 88
MCLR
OSC1
V
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
DD
RESET
On-chip
RC OSC
OST/PWRT
(Note 1)
Brown-out
V
Module
Detect
DD
WDT
Reset
Rise
OST
PWRT
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
10-bit Ripple Counter
10-bit Ripple Counter
WDT
Reset
Time-out
BODEN
Power-on Reset
External
RESET
SLEEP
Enable PWRT
Enable OST
on MCLR Reset during SLEEP, and on BOR. The TO
and PD bits are set or cleared differently in different
RESET situations, as indicated in Table 13-4. These
bits are used in software to determine the nature of the
RESET. See Table 13-6 for a full description of RESET
states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 13-4.
The PICmicro devices have a MCLR noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that internal RESET sources do not
drive MCLR pin low.
2000 Microchip Technology Inc.
S
R
Q
Chip Reset