PIC18F87J90-I/PT Microchip Technology, PIC18F87J90-I/PT Datasheet - Page 192

• Manufacturer Part Number: PIC18F87J90-I/PT
• Description: IC PIC MCU FLASH 128KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

control is not needed.
PIC18F87J90 FAMILY
17.3.3.4
In M3, the LCD regulator is completely disabled. Like
M2, LCD bias levels are tied to AV
using an external divider. The difference is that the inter-
nal voltage reference is also disabled and the bottom of
the ladder is tied to ground (V
value of the resistors, and the difference between V
and V
adjustment is possible. This configuration is also used
where the LCD’s current requirements exceed the
capacity of the charge pump and software contrast
FIGURE 17-5:
DS39933D-page 192
DD
Note 1: These values are provided for design guidance only; they should be optimized for the application by the
, determine the contrast range; no software
Bias Level at Pin
2: A potentiometer for manual contrast adjustment is optional; it may be omitted entirely.
M3 (Hardware Contrast)
LCDBIAS0
LCDBIAS1
LCDBIAS2
LCDBIAS3
PIC18F87J90
designer based on the actual LCD specifications.
RESISTOR LADDER CONNECTIONS FOR M3 CONFIGURATION
LCDBIAS3
LCDBIAS2
LCDBIAS1
LCDBIAS0
SS
AV
); see Figure 17-5. The
DD
DD
and are generated
V
DD
Static Bias
Static
AV
AV
AV
AV
DD
DD
SS
SS
(2)
SS
connected between some or all of the pins. A potentio-
meter can also be connected between LCDBIAS3 and
adjustment.
Depending on the bias type required, resistors are
V
M3 is selected by clearing the CKSEL<1:0> and CPEN
bits.
DD
Bias Type
1/2 AV
1/2 AV
1/2 Bias
1/2 Bias
AV
AV
to allow for hardware controlled contrast
DD
SS
DD
DD
10 k
10 k
(1)
(1)
 2010 Microchip Technology Inc.
1/3 AV
2/3 AV
1/3 Bias
AV
AV
1/3 Bias
DD
SS
DD
DD
10 k
10 k
10 k
(1)
(1)
(1)