PIC16C63A-04I/SS Microchip Technology, PIC16C63A-04I/SS Datasheet - Page 71

• Manufacturer Part Number: PIC16C63A-04I/SS
• Description: IC MCU OTP 4KX14 PWM 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63A-04I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
FIGURE 11-5:
TABLE 11-4:
0Bh,8Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76; always maintain these bits clear.
Address
2000 Microchip Technology Inc.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1).
Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
If interrupts are desired, set interrupt enable bits
RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
If 9-bit reception is desired, then set bit RX9.
Note:
RX (pin)
Rcv shift
reg
Rcv buffer reg
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
Shaded cells are not used for asynchronous reception.
INTCON
PIR1
RCSTA
RCREG USART Receive register
PIE1
TXSTA
SPBRG Baud Rate Generator register
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the
third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user’s firmware.
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
PSPIE
START
PSPIF
CSRC
SPEN
ASYNCHRONOUS RECEPTION
bit
Bit 7
GIE
(1)
(1)
bit0
ADIF
ADIE
Bit 6
PEIE
RX9
TX9
bit1
(2)
(2)
SREN
TXEN
RCIF
RCIE
Bit 5
T0IE
bit7/8
CREN
SYNC
INTE
Bit 4
TXIF
TXIE
STOP
bit
PIC16C63A/65B/73B/74B
Word 1
RCREG
START
SSPIF CCP1IF
SSPIE CCP1IE TMR2IE TMR1IE
RBIE
Bit 3
bit
—
—
bit0
5.
6.
7.
8.
9.
BRGH
FERR
Bit 2
T0IF
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
TMR2IF
bit7/8 STOP
OERR
TRMT
Word 2
RCREG
Bit 1
INTF
bit
TMR1IF
RX9D
TX9D
RBIF
Bit 0
START
bit
0000 000x
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
bit7/8
DS30605C-page 71
STOP
bit
0000 000u
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
all other
RESETS