DSPIC30F3010-30I/SP Microchip Technology, DSPIC30F3010-30I/SP Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F3010-30I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-30I/SP

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 20
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F301030ISP

dsPIC30F3010/3011
11. Output Compare Module
12. Quadrature Encoder Interface (QEI) Module
13. INT0, ADC and Sleep Mode
14. 8x PLL Mode
15. 10-bit ADC: Sampling Rate
16. Quadrature Encoder Interface (QEI) Module
17. I
18. I
19. I
20. I
21. I
22. I/O Port – Port Pin Multiplexed with IC1
DS80389B-page 2
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
The Index Pulse Reset mode of the QEI does not
work properly when used along with count error
detection. When counting upwards, the POSCNT
register will increment one extra count after the
index pulse is received. The extra count will
generate a false count error interrupt.
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero.
If 8x PLL mode is used, the input frequency range
is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
The 10-bit Analog-to-Digital Converter (ADC) has
a maximum sampling rate of 750 ksps.
The QEI module does not generate an interrupt in
a particular overflow condition.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
The I
operating as an I
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
2
2
2
2
2
C™ Module
C Module: 10-bit Addressing Mode
C Module
C Module: 10-bit addressing mode
C Module: 10-bit Addressing Mode
2
C module loses incoming data bytes when
2
C module is enabled, the dsPIC
2
2
C module is configured as a 10-bit
C module is configured for 10-bit
2
C devices, the A10 and A9 bits may
2
C slave.
®
DSC
23. ADC Module
24. Motor Control PWM – PWM Counter Register
25. Timer Module
26. PLL Lock Status Bit
The following sections describe the errata and work
around to these errata, where they may apply.
The port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
The ADC module has an offset error (greater than
the specification mentioned in the device data
sheet), when using an internal reference (AV
AV
PTMR does not continue counting down after
halting code execution in Debug mode.
Clock switching prevents the device from waking
up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
Oscillator Failure Trap even when the PLL is still
locked and functioning correctly.
SS
).
© 2008 Microchip Technology Inc.
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