DSPIC30F3014-30I/PT Microchip Technology, DSPIC30F3014-30I/PT Datasheet
DSPIC30F3014-30I/PT
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... Microchip Technology Inc. dsPIC30F3014/4013 Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70138F ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fractional/Integer Multiplier • All DSP Instructions are Single Cycle - Multiply-Accumulate (MAC) Operation • Single-Cycle ±16 Shift © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Peripheral Features: • High-Current Sink/Source I/O Pins: 25 mA/25 mA • Five 16-Bit Timers/Counters; Optionally Pair Up 16-Bit Timers into 32-Bit Timer modules • ...
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... CMOS Technology: • Low-Power, High-Speed Flash Technology • Wide Operating Voltage Range (2.5V to 5.5V) • Industrial and Extended Temperature Ranges • Low-Power Consumption dsPIC30F3014/4013 Controller Family Program Memory Device Pins Bytes Instructions dsPIC30F3014 40/44 24K 8K dsPIC30F4013 40/44 48K 16K DS70138F-page 2 ...
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... Pin Diagrams 40-Pin PDIP AN0/V AN1/V AN2/SS1/LVDIN/CN4/RB2 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 AV MCLR 1 40 +/CN2/RB0 AVss REF 2 39 -/CN3/RB1 AN9/RB9 REF 3 38 AN10/RB10 4 37 AN3/CN5/RB3 AN11/RB11 5 36 AN4/CN6/RB4 AN12/RB12 6 35 AN5/CN7/RB5 EMUC2/OC1/RD0 7 34 EMUD2/OC2/RD1 AN8/RB8 10 31 ...
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... TQFP U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 RF1 RF0 EMUD2/OC2/RD1 EMUC2/OC1/RD0 AN12/RB12 AN11/RB11 Note 1: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70138F-page EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKI dsPIC30F3014 AN8/RB8 27 7 PGD/EMUD/AN7/RB7 26 8 PGC/EMUC/AN6/OCFA/RB6 9 25 AN5/CN7/RB5 AN4/CN6/RB4 11 © 2008 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 44-Pin QFN U1RX/SDI1/SDA/RF2 1 U2TX/CN18/RF5 2 U2RX/CN17/RF4 3 RF1 4 RF0 EMUD2/OC2/RD1 9 EMUC2/OC1/RD0 10 AN12/RB12 11 Note 1: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 OSC2/CLKO/RC15 33 OSC1/CLKI dsPIC30F3014 DD 28 AN8/RB8 27 PGD/EMUD/AN7/RB7 26 PGC/EMUC/AN6/OCFA/RB6 25 AN5/CN7/RB5 24 AN4/CN6/RB4 23 DS70138F-page 5 ...
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... Pin Diagrams (Continued) 40-Pin PDIP AN0/V AN1/V AN2/SS1/LVDIN/CN4/RB2 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 44-Pin TQFP U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 C1TX/RF1 C1RX/RF0 EMUD2/OC2/RD1 EMUC2/OC1/RD0 AN12/COFS/RB12 AN11/CSDO/RB11 Note 1: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70138F-page 6 MCLR +/CN2/RB0 REF -/CN3/RB1 REF ...
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... Pin Diagrams (Continued) 44-Pin QFN U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 C1TX/RF1 C1RX/RF0 EMUD2/OC2/RD1 10 EMUC2/OC1/RD0 AN12/COFS/RB12 11 Note 1: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 1 33 OSC2/CLKO/RC15 2 32 OSC1/CLKI dsPIC30F4013 AN8/RB8 PGD/EMUD/AN7/RB7 8 26 PGC/EMUC/AN6/OCFA/RB6 9 25 AN5/IC8/CN7/RB5 ...
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... Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU Architecture Overview........................................................................................................................................................ 13 3.0 Memory Organization ................................................................................................................................................................. 23 4.0 Address Generator Units ............................................................................................................................................................ 35 5.0 Flash Program Memory .............................................................................................................................................................. 41 6.0 Data EEPROM Memory ............................................................................................................................................................. 47 7.0 I/O Ports ..................................................................................................................................................................................... 53 8.0 Interrupts .................................................................................................................................................................................... 59 9.0 Timer1 Module ........................................................................................................................................................................... 67 10.0 Timer2/3 Module ........................................................................................................................................................................ 71 11.0 Timer4/5 Module ....................................................................................................................................................................... 77 12.0 Input Capture Module ................................................................................................................................................................. 81 13.0 Output Compare Module ............................................................................................................................................................ 85 14.0 I2C™ ...
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... This document contains specific information for the dsPIC30F3014/4013 Digital Signal Controller (DSC) devices. The dsPIC30F3014/4013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F3014 and dsPIC30F4013, respectively. X Data Bus ...
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... FIGURE 1-2: dsPIC30F4013 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU Program Counter Stack Address Latch Control Logic Program Memory (48 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... I Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Buffer Description Type Analog Analog input channels. AN6 and AN7 are also used for device programming data and clock inputs, respectively. P Positive supply for analog module. ...
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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Name Type RA11 I/O RB0-RB12 I/O RC13-RC15 I/O RD0-RD3, RD8, RD9 I/O RF0-RF5 I/O SCK1 I/O SDI1 I SDO1 O SS1 I SCL I/O SDA I/O SOSCO O SOSCI I T1CK I T2CK I U1RX I U1TX O U1ARX I U1ATX REF ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can ...
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... The core does not support a multi-stage instruction pipeline. However, a single-stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors ...
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... AccA DSP Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. dsPIC30F3014/4013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 Program Space Visibility Page Address ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...
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... EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70138F-page 18 40-Bit Accumulator A 40-Bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2008 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2.4.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input ...
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... The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated if saturation is enabled. When ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70138F-page 22 © 2008 Microchip Technology Inc. ...
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... Table 3-1. Note that the program space address is incremented by two between succes- sive program words in order to provide compatibility with data space addressing. FIGURE 3-1: dsPIC30F3014 PROGRAM SPACE MEMORY MAP Reset – GOTO Instruction Reset – Target Address Interrupt Vector Table ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using Program 0 Space Visibility Using ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) © 2008 Microchip Technology Inc. dsPIC30F3014/4013 A set of table instructions are provided to move byte or word-sized data to and from program space. (See Figure 3-4 and Figure 3-5.) 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; ...
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... FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... PSVPAG is an 8-bit register, containing bits<22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). The memory map shown here is for a dsPIC30F4013 device. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Program Space 0x0000 (1) ...
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... Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent Linear Addressing space, X and Y spaces have contiguous addresses. FIGURE 3-7: dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2008 Microchip Technology Inc. dsPIC30F3014/4013 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 ...
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... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... A PC push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 ...
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... NOTES: DS70138F-page 34 © 2008 Microchip Technology Inc. ...
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... Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2008 Microchip Technology Inc. dsPIC30F3014/4013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x0800 0x0863 Start Addr = 0x0800 End Addr = 0x0863 Length = 0x0032 words © 2008 Microchip Technology Inc. dsPIC30F3014/4013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to) ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value A0 Decimal 0x0200 0x0100 ...
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... NOTES: DS70138F-page 40 © 2008 Microchip Technology Inc. ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F3014/4013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions or 96 bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the Table Pointer must be changed at each panel boundary ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F3014/4013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... LOADING WRITE LATCHES Example 5-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 5-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 5-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
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... NOTES: DS70138F-page 46 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3014/4013 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- sible for waiting for the appropriate duration of time before initiating another data EEPROM write/erase operation ...
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... Erasing Data EEPROM 6.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The write does not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EXAMPLE 6-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 TBLWTL W2 [ W0]++ , MOV #data2,W2 TBLWTL W2 [ W0]++ , MOV #data3,W2 TBLWTL W2 [ W0]++ , MOV #data4,W2 TBLWTL W2 [ W0]++ , MOV #data5,W2 TBLWTL W2 [ W0]++ , MOV #data6,W2 TBLWTL W2 [ W0]++ , MOV #data7,W2 TBLWTL W2 [ W0]++ ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 6.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70138F-page 52 © 2008 Microchip Technology Inc. ...
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... WR PORT Read LAT Read PORT © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Reads from the latch (LATx), read the latch. Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). ...
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... FIGURE 7-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR PORT Data Latch Read LAT Read PORT 7.2 ...
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... TABLE 7-1: dsPIC30F3014/4013 PORT REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — TRISB 02C6 — — — TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0001 1111 1111 1111 ...
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... Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor, in response to a Change-Of- State (COS) on selected input pins. This module is capable of detecting input Change-Of-States, even in Sleep mode, when the clocks are disabled. There are ...
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... TABLE 7-2: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014/4013 DEVICES (BITS 15-0) SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name CNEN1 00C0 — — — — — CNEN2 00C2 — — — — — CNPU1 00C4 — — — — — ...
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... NOTES: DS70138F-page 58 © 2008 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the con- trol and status flags for the processor exceptions ...
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... Table 8-1 and Table 8-2 list the interrupt numbers, corresponding interrupt sources and associated vector numbers for the dsPIC30F3014 and dsPIC30F4013 devices, respectively. Note 1: The natural order priority scheme has 0 as the highest priority and 53 as the lowest priority ...
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... LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority © 2008 Microchip Technology Inc. dsPIC30F3014/4013 8.2 Reset Sequence A Reset is not a true exception because the interrupt controller is not involved in the Reset process. The pro- cessor initializes its registers in response to a Reset which forces the PC to zero ...
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... Traps Traps can be considered as non-maskable interrupts, indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 8-1. They are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. Note: If the user does not intend to take correc- ...
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... The processor then loads the priority level for this © 2008 Microchip Technology Inc. dsPIC30F3014/4013 interrupt into the STATUS register. This action disables all lower priority interrupts until the completion of the Interrupt Service Routine. ...
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... Fast Context Saving A context saving option is available using shadow reg- isters. Shadow registers are provided for the DC, N, OV, Z and C bits in SR, and the registers, W0 through W3. The shadows are only one level deep. The shadow registers are accessible using the PUSH.S and POP.S instructions only ...
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... TABLE 8-3: dsPIC30F3014 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF IFS1 0086 — — — ...
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TABLE 8-4: dsPIC30F4013 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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... SOSCO/ T1CK LPOSCEN SOSCI © 2008 Microchip Technology Inc. dsPIC30F3014/4013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-Bit Timer Mode: In the 16-Bit Timer mode, the timer increments on every instruction cycle match value preloaded into the Period register, PR1, then resets to ‘ ...
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... Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit, TGATE (T1CON<6>), must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0) ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt is generated, if enabled ...
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... TABLE 9-1: dsPIC30F3014/4013 TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. ...
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... These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD Write TMR2 Read TMR2 16 Reset ADC Event Trigger Equal 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
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... ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK Note: T3CK pin does not exist on dsPIC30F3014/4013 devices. The block diagram shown here illustrates the schematic of Timer3 as implemented on the dsPIC30F6014 device. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 PR2 Comparator x 16 TMR2 TGATE Q D ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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... TABLE 10-1: dsPIC30F3014/4013 TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ ...
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... NOTES: DS70138F-page 76 © 2008 Microchip Technology Inc. ...
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... T4CK Note: Timer Configuration bit, T32 (T4CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The Timer4/5 module is similar in operation to the Timer2/3 module. differences: • The Timer4/5 module does not support the ADC event trigger feature • ...
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... ADC Event Trigger Equal Reset 0 T5IF Event Flag 1 TGATE T5CK Note: In the dsPIC30F3014 device, there is no T5CK pin. Therefore, in this device the following modes should not be used for Timer5: 2: TCS = 1 (16-bit counter) 3: TCS = 0, TGATE = 1 (gated time accumulation) DS70138F-page 78 PR4 Comparator x 16 TMR4 TGATE Q ...
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TABLE 11-1: dsPIC30F4013 TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: ...
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... NOTES: DS70138F-page 80 © 2008 Microchip Technology Inc. ...
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... These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain capture channels (i.e., the maximum value 8). The dsPIC30F3014 device contains 2 capture channels while the dsPIC30F4013 device contains 4 capture channels. 12.1 Simple Capture Event Mode ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow ...
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... TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. ...
Page 86
... NOTES: DS70138F-page 84 © 2008 Microchip Technology Inc. ...
Page 87
... These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC DSC devices contain compare channels (i.e., the maximum value 8). The dsPIC30F3014 device contains 2 compare channels while the dsPIC30F4013 device contains 4 compare channels. OCxRS and OCxR in Figure 13-1 represent the Dual Compare registers ...
Page 88
... Simple Output Compare Match Mode When control bits, OCM<2:0> (OCxCON<2:0>) = 001, 010 or 011, the selected output compare channel is configured for one of three simple Output Compare Match modes: • Compare forces I/O pin low • Compare forces I/O pin high • ...
Page 89
... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • ...
Page 90
... TABLE 13-1: dsPIC30F3014 OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — Legend: — = unimplemented bit, read as ‘0’ ...
Page 91
... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 14.1.1 VARIOUS I The following types • slave operation with 7-bit addressing 2 • slave operation with 10-bit addressing 2 • ...
Page 92
... FIGURE 14-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70138F-page 90 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control ...
Page 93
... SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 94
... MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 14.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching ...
Page 95
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device-specific or a general call address. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2 14. Master Support As a master device, six operations are supported: ...
Page 96
... I C MASTER RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (I2CCON<3>). The I module must be Idle before the RCEN bit is set; other- wise, the RCEN bit is disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin ACK and data are shifted into the I2CRSR on the rising edge of each clock ...
Page 97
... TABLE 14-2: dsPIC30F3014/4013 I C REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN I2CSTAT 0208 ACKSTAT TRSTAT — ...
Page 98
... NOTES: DS70138F-page 96 © 2008 Microchip Technology Inc. ...
Page 99
... SCL transitions while SPIROV is ‘1’, effectively disabling the module until SPIxBUF is read by user software. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) are moved to the receive buffer ...
Page 100
... Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit, FRMEN, enables framed SPI support and causes the SSx pin to perform the Frame Synchronization pulse (FSYNC) function. The control bit, SPIFSD, determines whether ...
Page 101
... The transmitter and receiver stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 15.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT<13>) determines if the SPI module stops or continues on Idle ...
Page 102
... TABLE 15-1: dsPIC30F3014/4013 SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. ...
Page 103
... UxTX or UxATX if ALTIO = 1 Parity Note © 2008 Microchip Technology Inc. dsPIC30F3014/4013 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 104
... FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 0 UxRX · Start bit Detect or UxARX · Parity Check · Stop bit Detect if ALTIO = 1 · Shift Clock Generation · Wake Logic DS70138F-page 102 Internal Data Bus 16 Write Read URX8 UxRXREG Low Byte ...
Page 105
... The STSEL bit determines whether one or two Stop bits are used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F3014/4013 16.3 Transmitting Data 16.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 106
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 107
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this special mode in which a 9th bit (URX8) value of ‘ ...
Page 108
... Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit ...
Page 109
... U1BRG 0214 Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 16-2: dsPIC30F3014/4013 UART2 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name U2MODE ...
Page 110
... NOTES: DS70138F-page 108 © 2008 Microchip Technology Inc. ...
Page 111
... CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 112
... FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS (2) (2) TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic (1) CiTX Note refers to a particular CAN module (CAN1 or CAN2). 2: These are conceptual groups of registers, not SFR names by themselves. ...
Page 113
... Module Disable mode. The I/O pins revert to normal I/O function when the module is in the Module Disable mode. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 114
... Message Reception 17.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, denoted as RXB0 and RXB1, that can essentially instantaneously receive a complete message from the protocol engine ...
Page 115
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 116
... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXnIF flags are read to determine which transmit buffer is available and caused the interrupt ...
Page 117
... The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg © 2008 Microchip Technology Inc. dsPIC30F3014/4013 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that respec fixed tive bit ...
Page 118
TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1RXF0SID 0300 — — — C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> C1RXF1SID 0308 — — ...
Page 119
TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B1 0356 Transmit Buffer 1 Byte 1 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C ...
Page 120
... NOTES: DS70138F-page 118 © 2008 Microchip Technology Inc. ...
Page 121
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled. ...
Page 122
... FIGURE 18-1: DCI MODULE BLOCK DIAGRAM F OSC Word-Size Selection bits Frame Length Selection bits DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70138F-page 120 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer Control Unit ...
Page 123
... Note: The COFSG control bits have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 18.3.4 FRAME SYNC MODE CONTROL BITS The type of Frame Sync signal is selected using the Frame ...
Page 124
... SLAVE FRAME SYNC OPERATION When the DCI module is operating as a Frame Sync slave (COFSD = 1), data transfers are controlled by the Codec device attached to the DCI module. The COFSM control bits control how the DCI module responds to incoming COFS signals. In the Multichannel mode, a new data frame transfer begins one CSCK cycle after the COFS pin is sampled high (see Figure 18-2) ...
Page 125
... When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet the device timing requirements. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 EQUATION 18-2: The required bit clock frequency is determined by the system sampling rate and frame size. Typical bit clock ...
Page 126
... SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data is sampled on the falling edge of the CSCK signal. The AC-Link protocols and most multichannel formats require that data be sampled on the falling edge of the CSCK signal ...
Page 127
... DCI module. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. The TMPTY bit is set when the contents of the transmit buffer registers are transferred to the transmit shadow registers ...
Page 128
... SLOT STATUS BITS The SLOT<3:0> status bits in the DCISTAT SFR indi- cate the current active time slot. These bits correspond to the value of the Frame Sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers ...
Page 129
... Synchronization signal marks the boundary of a new data word transfer. The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2 18.7 FRAME AND DATA WORD LENGTH SELECTION ...
Page 130
... TABLE 18-2: dsPIC30F3014/4013 DCI REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DCICON1 0240 DCIEN — DCISIDL — DCICON2 0242 — — — — DCICON3 0244 — — — — DCISTAT 0246 — — — — TSCON 0248 TSE15 TSE14 ...
Page 131
... The ADCHS, ADPCFG and ADCSSL registers allow the application to configure AN13-AN15 as analog input pins. Since these pins are not physically present on the device, conversion results from these pins will read ‘0’. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The A/D module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • ...
Page 132
... A/D Result Buffer The module contains a 16-word, dual port read-only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data for- mats. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 133
... ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “Electrical Characteristics” for minimum T other operating conditions ...
Page 134
... ADC Speeds The dsPIC30F 12-bit ADC specifications permit a maximum of 200 ksps sampling rate. The table below summarizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES dsPIC30F 12-Bit ADC Conversion Rates ...
Page 135
... Figure 19-2 depicts the recommended circuit for the conversion rates above 200 ksps. The dsPIC30F3014 is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC 0.1 μF 0.01 μF Note 1: Ensure adequate bypass capacitors are provided on each V The configuration procedures below give the required setup values for the conversion speeds above 100 ksps ...
Page 136
... FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 ksps, AUTO-SAMPLE START SAMPLING TIME T SAMP = ADCLK SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM 19.8 A/D Acquisition Requirements The analog input model of the 12-bit A/D converter is shown in Figure 19-4. The total sampling time for the A function of the internal amplifier settling time and the holding capacitor charge time ...
Page 137
... Integer 0 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 If the A/D interrupt is enabled, the device wakes up from Sleep. If the A/D interrupt is not enabled, the A/D module is then turned off, although the ADON bit remains set ...
Page 138
... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (V converted ...
Page 139
TABLE 19-2: A/D CONVERTER REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — ...
Page 140
... NOTES: DS70138F-page 138 © 2008 Microchip Technology Inc. ...
Page 141
... In the Idle mode, the clock sources are still active but the CPU is shut off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 142
... TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 143
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F3014/4013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer Clock Switching Secondary Osc ...
Page 144
... Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups, b) and FPR<4:0> Configuration bits that select one of 13 oscillator choices within the primary group. ...
Page 145
... If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multiplier (respectively) is applied. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Note: When a 16x PLL is used, the FRC frequency must not be tuned to a frequency greater than 7.5 MHz. ...
Page 146
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (clock switch and monitor selection bits) in the FOSC Device Configuration register. If the FSCM function is enabled, ...
Page 147
... Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Note: The description of the OSCCON and OSCTUN SFRs, as well as the FOSC Con- figuration register provided in this section are applicable only to the dsPIC30F3014 and dsPIC30F4013 dsPIC30F product family. R-y U-0 R/W-y — ...
Page 148
... REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clearable by application FSCM has detected clock failure 0 = FSCM has NOT detected clock failure Reset on POR or BOR. Reset when a valid clock switching sequence is initiated. Set when clock fail ...
Page 149
... Center frequency, oscillator is running at calibrated frequency 1111 = 1110 = 1101 = 1100 = 1011 = 1010 = 1001 = 1000 = Minimum frequency © 2008 Microchip Technology Inc. dsPIC30F3014/4013 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — TUN<3:0> Unimplemented bit, read as ‘0’ ...
Page 150
... REGISTER 20-3: FOSC: OSCILLATOR CONFIGURATION REGISTER — — — bit 23 R/P R/P U FCKSM<1:0> — bit — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘0’ bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits ...
Page 151
... Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 152
... FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 153
... Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source based on the device Configuration bit values (FOS<2:0> and FPR< ...
Page 154
... Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table means that all the bits are negated prior to the action specified in the condition column. TABLE 20-5: ...
Page 155
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2008 Microchip Technology Inc. dsPIC30F3014/4013 20.7 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV; ...
Page 156
... Any interrupt that is individually enabled (using the cor- responding IE bit) and meets the prevailing priority level can wake-up the processor. The processor processes the interrupt and branch to the ISR. The SLEEP status bit in the RCON register is set upon wake-up. Note: ...
Page 157
... Note: In the dsPIC30F3014 device, the T4MD, T5MD, IC7MD, IC8MD, OC3MD, OC4MD and DCIMD are readable and writable, and are read as “1” when set. © 2008 Microchip Technology Inc. ...
Page 158
... Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: Reset state depends on type of Reset. 3: Reset state depends on Configuration bits. 4: These bits are not available in dsPIC30F3014 devices. TABLE 20-8: DEVICE CONFIGURATION REGISTER MAP File Name Addr. Bits 23-16 Bit 15 ...
Page 159
... The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 160
... Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the ...
Page 161
... Y data space prefetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Description DS70138F-page 159 ...
Page 162
... TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Mnemoni Assembly Syntax # c 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND ...
Page 163
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 # of Description Words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 164
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemoni Assembly Syntax # c 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R ...
Page 165
... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2008 Microchip Technology Inc. dsPIC30F3014/4013 # of Description Words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * ...
Page 166
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemoni Assembly Syntax # c 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 69 SETM SETM f SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 71 SL ...
Page 167
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F3014/4013 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 168
... MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 169
... Microchip Technology Inc. dsPIC30F3014/4013 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 170
... PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 171
... Microchip Technology Inc. dsPIC30F3014/4013 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ...................................................................................................± pin, inducing currents greater than 80 mA, may cause latch-up. ...
Page 172
... TABLE 23-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F3014-30I dsPIC30F4013-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F3014-20E dsPIC30F4013-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: × ∑ – I INT I/O Pin power dissipation: ...
Page 173
... All I/O pins are configured as inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, program memory and data memory DD are operational. No peripheral modules are operating. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ ...
Page 174
... TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter Typical Max No. (1) Operating Current ( DC51a 1.4 3 DC51b 1.5 3 DC51c 1.5 3 DC51e 3 5 DC51f 3 5 DC51g 3 5 DC50a 4 6 DC50b 4 6 DC50c 4 6 DC50e 8 11 DC50f 8 11 DC50g 8 11 DC43a 7 11 DC43b ...
Page 175
... The Δ current is the additional current consumed when the module is enabled. This current should be 2: added to the base I current. PD © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40° ...
Page 176
... TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Input Low Voltage IL DI10 I/O Pins: with Schmitt Trigger Buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 177
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS V DD LV10 LVDIF (LVDIF set by hardware) © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min Typ ...
Page 178
... TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL DC CHARACTERISTICS Param Symbol Characteristic No. LV10 V LVDL Voltage on V PLVD Transition High-to-Low LV15 V External LVD Input Pin LVDIN Threshold Voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: ...
Page 179
... EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 180
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 23-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 ...
Page 181
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 182
... TABLE 23-15: PLL JITTER Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. TABLE 23-16: INTERNAL CLOCK TIMING EXAMPLES Clock F OSC Oscillator ...
Page 183
... AC CHARACTERISTICS Operating temperature Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2008 Microchip Technology Inc. dsPIC30F3014/4013 -40°C ≤ -40°C ≤ Min Typ Max Units (1) -40°C ≤ T — — ±2.00 % -40° ...
Page 184
... FIGURE 23-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 23-3 for load conditions. TABLE 23-19: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port Output Rise Time IO DO32 ...
Page 185
... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 Oscillator Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 SY10 SY20 SY13 SY13 DS70138F-page 183 ...
Page 186
... TABLE 23-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY10 TmcL MCLR Pulse Width (low) SY11 T Power-up Timer Period PWRT SY12 T Power-on Reset Delay POR SY13 T I/O High-Impedance from MCLR ...
Page 187
... TCS (T1CON<1>) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: Timer1 is a Type A. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 188
... TABLE 23-23: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TB10 TtxH TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, TB20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: Timer2 and Timer4 are Type B ...
Page 189
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 190
... FIGURE 23-11: OCx/PWM MODULE TIMING CHARACTERISTICS OCFA/OCFB OC15 OCx TABLE 23-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OC15 T Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 191
... CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 CS20 CS21 70 LSb ...
Page 192
... TABLE 23-28: DCI MODULE (MULTICHANNEL CHARACTERISTICS Param Symbol Characteristic No. CS10 Tc CSCK Input Low Time SCKL (CSCK pin is an input) CSCK Output Low Time (CSCK pin is an output) CS11 Tc CSCK Input High Time SCKH (CSCK pin is an input) CSCK Output High Time ...
Page 193
... DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 SYNC (COFS) CS80 MSb LSb SDOx (CSDO) MSb In SDIx (CSDI) CS65 CS66 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 CS62 CS21 CS71 CS72 CS76 CS76 CS75 CS20 CS70 CS75 LSb DS70138F-page 191 ...
Page 194
... TABLE 23-29: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. CS60 T BIT_CLK Low Time BCLKL CS61 T BIT_CLK High Time BCLKH CS62 T BIT_CLK Period BCLK CS65 T Input Setup Time to SACL Falling Edge of BIT_CLK CS66 T Input Hold Time from HACL ...
Page 195
... SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) SDO MSb X SP40 SP30,SP31 SDI X MSb In SP41 Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ ( — — — ...
Page 196
... TABLE 23-31: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SP10 TscL SCK Output Low Time X SP11 TscH SCK Output High Time X SP20 TscF SCK Output Fall Time X SP21 TscR SCK Output Rise Time X SP30 TdoF SDO ...
Page 197
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 SP70 SP72 SP73 SP73 SP72 MSb ...
Page 198
... FIGURE 23-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb In SP41 SP40 Note: Refer to Figure 23-3 for load conditions. DS70138F-page 196 SP70 SP72 SP73 SP35 SP73 SP72 ...
Page 199
... The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...
Page 200
... FIGURE 23-18: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 23-3 for load conditions. 2 FIGURE 23-19: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 ...