PIC18F4423-I/PT Microchip Technology, PIC18F4423-I/PT Datasheet - Page 19
![IC PIC MCU FLASH 8KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4423-I/PT
Manufacturer Part Number
PIC18F4423-I/PT
Description
IC PIC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18F4423-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 12-bit
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
Rohs Compliant
Yes
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4423-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4423-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.5
The code sequence detailed in Table 3-5 should be
used, except that the address used in “Step 2” will be in
the range of 000000h to 0007FFh.
TABLE 3-9:
FIGURE 3-8:
© 2005 Microchip Technology Inc.
Step 1: Enable writes and direct access to config memory.
Step 2
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
1111
0000
4-Bit
(1)
: Set Table Pointer for config byte to be written. Write even/odd addresses.
Boot Block Programming
Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration
bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.
8E A6
8C A6
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB ignored><LSB>
00 00
0E 01
6E F6
<MSB><LSB ignored>
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
CONFIGURATION PROGRAMMING FLOW
Data Payload
Delay P9 and P10
Time for Write
Configuration
Load Even
Program
Address
Done
Start
LSB
BSF
BSF
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
MOVLW 01h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
PIC18F2423/2523/4423/4523
EECON1, EEPGD
EECON1, CFGS
3.6
Unlike code memory, the Configuration bits are
programmed a byte at a time. The Table Write, Begin
Programming 4-bit command (‘1111’) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses and
the MSB will be written to odd addresses. The code
sequence to program two consecutive configuration
locations is shown in Table 3-9.
Note:
Core Instruction
Configuration Bits Programming
Delay P9 and P10
The address must be explicitly written for
each byte programmed. The addresses
can not be incremented in this mode.
Time for Write
Configuration
Load Odd
Program
Address
Start
MSB
Done
DS39759A-page 19