PIC18F4423-I/P Microchip Technology, PIC18F4423-I/P Datasheet - Page 83

• Manufacturer Part Number: PIC18F4423-I/P
• Description: IC PIC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4423-I/P

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
© 2007 Microchip Technology Inc.
PROGRAM_MEMORY1
Req
Seq
WRITE_BUFFER_BACK2
WRITE_BYTE_TO_HREGS2
PROGRAM_MEMORY2
Req
Seq
MOVWF
MOVLW
MOVWF
MOVLW
BSF
BCF
BSF
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVLW
MOVWF
MOVFF
MOVWF
TBLWT+*
DECFSZ COUNTER, F
BRA WRITE_BYTE_TO_HREGS2
BSF
BCF
BSF
BCF
MOVLW
MOVWF
BSF
BSF
BCF
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
EECON2
0Aah
EECON2
0AAh
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
D’32’
COUNTER
POSTINC0, WREG
TABLAT
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PIC18F2423/2523/4423/4523
; write 55h
; write 55h
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
; write remaining 32 bytes to Flash
; get low byte of buffer data
; present data to table latch
; short write to holding
; register using pre-increment
; loop until buffers are full
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
; number of bytes in holding register
Preliminary
6.5.4
To protect against unintended and spurious writes to
Flash program memory, the write initiate sequence
must be followed. In Example 6-3, the “Required
Sequence” acts to protect memory from unintended
writes by requiring this very specific sequence of five
instructions. This sequence must be executed exactly
as shown or the write will not occur.
6.6
Additional protection may be implemented using the
code protection features described in Section 23.5
“Program Verification and Code Protection”.
Flash Program Operation During
Code Protection
PROTECTION AGAINST
SPURIOUS WRITES
DS39755B-page 81