PIC32MX420F032H-40I/MR Microchip Technology, PIC32MX420F032H-40I/MR Datasheet - Page 56

• Manufacturer Part Number: PIC32MX420F032H-40I/MR
• Description: IC PIC MCU FLASH 32KX32 64-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX420F032H-40I/MR

• Core Size: 32-Bit
• Program Memory Size: 32KB (32K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 40MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC32
• Ram Memory Size: 8KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: EUSART, I2C, SPI, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, JTAG, SPI, TWI, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-9:
Legend:
Note
3000 OC1CON
3010
3020
3200 OC2CON
3210
3220
3400 OC3CON
3410
3420
3600 OC4CON
3610
3620
3800 OC5CON
3810
3820
1:
OC1RS
OC2RS
OC3RS
OC4RS
OC5RS
OC1R
OC2R
OC3R
OC4R
OC5R
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
OUTPUT COMPARE1-5 REGISTERS MAP
31/15
ON
ON
ON
ON
ON
—
—
—
—
—
30/14
FRZ
FRZ
FRZ
FRZ
FRZ
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
SIDL
SIDL
—
—
—
—
—
28/12
—
—
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
—
—
26/10
—
—
—
—
—
—
—
—
—
—
(1)
25/9
—
—
—
—
—
—
—
—
—
—
24/8
OC1RS<31:0>
OC2RS<31:0>
OC3RS<31:0>
OC4RS<31:0>
OC5RS<31:0>
—
—
—
—
—
—
—
—
—
—
OC1R<31:0>
OC2R<31:0>
OC3R<31:0>
OC4R<31:0>
OC5R<31:0>
Bits
23/7
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
OC32
OC32
OC32
OC32
OC32
21/5
—
—
—
—
—
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
20/4
—
—
—
—
—
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
19/3
—
—
—
—
—
18/2
—
—
—
—
—
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
17/1
—
—
—
—
—
16/0
—
—
—
—
—
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx