DSPIC33FJ128GP202-I/MM Microchip Technology, DSPIC33FJ128GP202-I/MM Datasheet - Page 49
![IC DSPIC MCU/DSP 128K 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ128GP202-I/MM
Manufacturer Part Number
DSPIC33FJ128GP202-I/MM
Description
IC DSPIC MCU/DSP 128K 28-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ128GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 49 of 402
- Download datasheet (3Mb)
TABLE 4-7:
TABLE 4-8:
TABLE 4-9:
OC1RS
OC1R
OC1CON
OC2RS
OC2R
OC2CON
OC3RS
OC3R
OC3CON
OC4RS
OC4R
OC4CON
Legend:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
SFR Name
SFR Name
SFR Name
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
020A
020C
Addr
SFR
0200
0202
0204
0206
0208
0220
0222
0224
0226
0228
SFR
Addr
0180
0182
0184
0186
0188
018A
018C
018E
0190
0192
0194
0196
SFR
OUTPUT COMPARE REGISTER MAP
I2C1 REGISTER MAP
UART1 REGISTER MAP
ACKSTAT
UTXISEL1
UARTEN
Bit 15
I2CEN
Bit 15
Bit 15
—
—
—
—
—
—
—
—
—
—
—
TRSTAT
UTXINV UTXISEL0
Bit 14
Bit 14
Bit 14
—
—
—
—
—
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
I2CSIDL
Bit 13
Bit 13
Bit 13
USIDL
—
—
—
—
—
—
—
—
Bit 12
SCLREL
Bit 12
Bit 12
—
—
—
—
IREN
—
—
—
—
—
—
—
—
—
Bit 11
UTXBRK
RTSMD
IPMIEN
—
—
—
—
Bit 11
Bit 11
—
—
—
—
—
—
—
—
Bit 10
—
—
—
—
UTXEN
Bit 10
Bit 10
A10M
BCL
—
—
—
—
—
—
—
—
Bit 9
—
—
—
—
UTXBF
GCSTAT
UEN1
DISSLW
Bit 9
Bit 9
—
—
Output Compare 1 Secondary Register
Output Compare 2 Secondary Register
Output Compare 3 Secondary Register
Output Compare 4 Secondary Register
—
—
—
Baud Rate Generator Prescaler
Output Compare 1 Register
Output Compare 2 Register
Output Compare 3 Register
Output Compare 4 Register
Bit 8
—
—
—
—
TRMT
UEN0
UTX8
URX8
Bit 8
ADD10
SMEN
Bit 8
—
—
Bit 7
—
—
—
—
WAKE
Bit 7
IWCOL
GCEN
URXISEL<1:0>
Bit 7
Bit 6
LPBACK
—
—
—
—
STREN
I2COV
Bit 6
Bit 6
Bit 5
Address Mask Register
—
—
—
—
ACKDT
ABAUD
ADDEN
Baud Rate Generator Register
Address Register
Bit 5
Bit 5
D_A
UART Received Register
UART Transmit Register
OCFLT
OCFLT
OCFLT
OCFLT
Bit 4
URXINV
ACKEN
RIDLE
Transmit Register
Bit 4
Receive Register
Bit 4
P
OCTSEL
OCTSEL
OCTSEL
OCTSEL
Bit 3
RCEN
BRGH
PERR
Bit 3
Bit 3
S
Bit 2
FERR
Bit 2
R_W
Bit 2
PEN
PDSEL<1:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
RSEN
OERR
Bit 1
Bit 1
Bit 1
RBF
URXDA
STSEL
Bit 0
Bit 0
SEN
Bit 0
TBF
Resets
Resets
0000
00FF
0000
1000
0000
0000
0000
Resets
0000
0110
xxxx
0000
0000
All
All
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
All
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