PIC24HJ64GP506-I/PT Microchip Technology, PIC24HJ64GP506-I/PT Datasheet - Page 9
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24HJ64GP506-I/PT
Manufacturer Part Number
PIC24HJ64GP506-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ256GP206-IPT.pdf
(58 pages)
Specifications of PIC24HJ64GP506-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
3-Wire/I2C/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
13
Operating Supply Voltage
0 V to 2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
18-ch x 12-bit
Controller Family/series
PIC24
No. Of I/o's
53
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
Embedded Interface Type
CAN, I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP506-I/PT
Manufacturer:
Microchip Technology
Quantity:
352
Company:
Part Number:
PIC24HJ64GP506-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24HJ64GP506-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
13. Module: I
14. Module: INT0, ADC and Sleep/Idle Mode
15. Module: Doze Mode and Traps
16. Module: JTAG Programming
17. Module: UART
© 2008 Microchip Technology Inc.
The Bus Collision Status bit (BCL) does not get set
when a bus collision occurs during a Restart or
Stop event. However, the BCL bit gets set when a
bus collision occurs during a Start event.
Work around
None.
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep or Idle mode if the
SMPI bits are non-zero. This means that if the
ADC is configured to generate an interrupt after a
certain number of INT0 triggered conversions, the
ADC conversions will not be triggered and the
device will remain in Sleep. The ADC will perform
conversions and wake-up the device only if it is
configured to generate an interrupt after each INT0
triggered conversion (SMPI<3:0> = 0000).
Work around
None. If ADC event trigger from the INT0 pin is
required, initialize SMPI<3:0> to ‘0000’ (interrupt
on every conversion).
The address error trap, stack error trap, math error
trap and DMA error trap will not wake-up a device
from Doze mode.
Work around
None.
JTAG programming does not work.
Work around
None.
With the parity option enabled, a parity error,
indicated by the PERR bit (UxSTA<3>) being set,
may occur if the Baud Rate Generator contains an
odd value. This affects both even and odd parity
options.
Work around
Load the Baud Rate Generator register, UxBRG,
with an even value, or disable the peripheral’s
parity option by loading either 0b00 or 0b11 into
the Parity and Data Selection bits, PDSEL<1:0>
(UxMODE<2:1>).
2
C
PIC24HJXXXGPX06/X08/X10
18. Module: UART
19. Module: UART
20. Module: UART
21. Module: UART
The Receive Buffer Overrun Error Status bit,
OERR (UxSTA<1>), may get set before the UART
FIFO has overflowed. After the fourth byte is
received by the UART, the FIFO is full. The OERR
bit should set after the fifth byte has been received
in the UART shift register. Instead, the OERR bit
may set after the fourth received byte with the
UART Shift register empty.
Work around
After four bytes have been received by the UART,
the UART Receiver Interrupt Flag bit, U1RXIF
(IFS0<11>) or U2RXIF (IFS1<14>), will be set,
indicating the UART FIFO is full. The OERR bit
may also be set. After reading the UART receive
buffer, UxRXREG, four times to clear the FIFO,
clear both the OERR and UxRXIF bits in software.
UART receptions may be corrupted if the Baud
Rate Generator is set up for 4x mode (BRGH = 1).
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
The UTXISEL0 bit (UxSTA<13>) is always read as
zero regardless of the value written to it. The bit
can be written to either a ‘0’ or ‘1’, but will always
be read as zero. This will affect read-modify-write
operations such as bitwise or shift operations.
Using a read-modify-write instruction on the
UxSTA register (e.g., BSET, BLCR) will always
write the UTXISEL0 bit to zero.
Work around
If a UTXISEL0 value of ‘1’ is needed, avoid using
read-modify-write instructions on the UxSTA
register. Copy the UxSTA register to a temporary
variable and set UxSTA<13> prior to performing
read-modify-write operations. Copy the new value
back to the UxSTA register.
The auto-baud feature may not calculate the
correct baud rate when the High Baud Rate Enable
bit, BRGH, is set. With the BRGH bit set, the baud
rate calculation used is the same as BRG = 0.
Work around
If the auto-baud feature is needed, use the Low
Baud Rate mode by clearing the BRGH bit.
DS80280G-page 9