PIC18F4331-I/PT Microchip Technology, PIC18F4331-I/PT Datasheet - Page 15
![IC PIC MCU FLASH 4KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4331-I/PT
Manufacturer Part Number
PIC18F4331-I/PT
Description
IC PIC MCU FLASH 4KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18F4331-I/PT
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
9 bit
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Details
Other names
PIC18F4331-I/PTR
PIC18F4331-I/PTR
PIC18F4331-I/PTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4331-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4331-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.2.1
The programming example presented in Section 3.2
utilizes multi-panel programming. This technique
greatly decreases the total amount of time necessary to
completely program a device and is the recommended
method of completely programming a device.
There may be situations, however, where it is advanta-
geous to limit writes to a single panel. In such cases,
the user only needs to disable the multi-panel write
feature of the device by appropriately configuring the
Programming Control register located at 3C0006h.
The single panel that will be written will automatically
be enabled based on the value of the table pointer.
3.2.2
All of the programming examples up to this point have
assumed that the device has been bulk erased prior to
programming (see Section 3.1). It may be the case,
however, that the user wishes to modify only a section
of an already programmed device.
The minimum amount of data that can be written to the
device is 8 bytes. This is accomplished by placing the
device in Single Panel Write mode (see Section 3.2.1),
loading the 8-byte write buffer for the panel, and then
initiating a write sequence. In this case, however, it is
assumed that the address space to be written already
has data in it (i.e., it is not blank).
2010 Microchip Technology Inc.
Note:
SINGLE PANEL PROGRAMMING
Even though multi-panel writes are dis-
abled, the user must still fill the 8-byte
write buffer for the given panel.
MODIFYING CODE MEMORY
PIC18F2331/2431/4331/4431
The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device must
be placed in Single Panel Write mode. The EECON1
register must then be used to erase the 64-byte target
space prior to writing the data.
When using the EECON1 register to act on code
memory, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases), and this must
be done prior to initiating a write sequence. The FREE
bit must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the table pointer.
The erase sequence is initiated by the setting the WR
bit (EECON1<1> = 1). It is strongly recommended that
the WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur.
The erase will begin on the falling edge of the 4th SCLK
after the WR bit is set. After the erase sequence termi-
nates, SCLK must still be held low for the time specified
by parameter #P10 to allow high voltage discharge of
the memory array.
DS30500B-page 15