PIC18F4331-I/PT Microchip Technology, PIC18F4331-I/PT Datasheet - Page 233

• Manufacturer Part Number: PIC18F4331-I/PT
• Description: IC PIC MCU FLASH 4KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4331-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F4331-I/PTR; PIC18F4331-I/PTR

19.2.3
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 19-1) begins whenever a Start bit is received and
the ABDEN bit is set. The calculation is self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Detect
must receive a byte with the value of 55h (ASCII “U”,
which is also the LIN bus Sync character) in order to
calculate the proper bit rate. The measurement takes
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming
signal. After a Start bit, the SPBRG begins counting up,
using the preselected clock source on the first rising
edge of RX. After eight bits on the RX pin, or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH:SPBRG registers.
Once the 5th edge is seen (should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
FIGURE 19-1:
© 2007 Microchip Technology Inc.
BRG Clock
BRG Value
Note 1:
ABDEN bit
(Interrupt)
SPBRGH
RCIF bit
RCREG
SPBRG
RX Pin
Read
AUTO-BAUD RATE DETECT
The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
Set by user
XXXXh
AUTOMATIC BAUD RATE CALCULATION
0000h
Start
PIC18F2331/2431/4331/4431
Bit 0
XXXXh
XXXXh
Edge #1
Preliminary
Bit 1
Bit 2
Edge #2
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 19-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. RCREG content should be discarded.
TABLE 19-4:
BRG16
Note:
Note 1: If the WUE bit is set with the ABDEN bit,
Bit 3
0
0
1
1
2: It is up to the user to determine that the
Bit 4
Edge #3
BRGH
During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of the BRG16 setting.
Auto-Baud Rate Detection will occur on
the byte following the Break character
(see Section 19.3.4 “Auto-Wake-up on
Sync Break Character”).
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system tim-
ing and communication baud rates must
be taken into consideration when using the
Auto-Baud Rate Detection feature.
0
1
0
1
Bit 5
BRG COUNTER CLOCK
RATES
Bit 6
Edge #4
BRG Counter Clock
Bit 7
F
F
F
F
OSC
OSC
OSC
OSC
DS39616C-page 231
Stop Bit
Edge #5
/512
/256
/128
/32
Auto-Cleared
001Ch
1Ch
00h