DSPIC33FJ128MC202-I/SP Microchip Technology, DSPIC33FJ128MC202-I/SP Datasheet - Page 197

• Manufacturer Part Number: DSPIC33FJ128MC202-I/SP
• Description: IC DSPIC MCU/DSP 128K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC202-I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SPDIP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

13.0
FIGURE 13-1:
FIGURE 13-2:
© 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
TxCK
2: Some registers and associated bits
TIMER2/3 AND TIMER4/5
FEATURE
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 11. Timers”
(DS70205) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
TxCK
the
F
TYPE B TIMER BLOCK DIAGRAM (x = 2 or 4)
TYPE C TIMER BLOCK DIAGRAM (x = 3 or 5)
CY
Sync
dsPIC33FJ32MC302/304,
TCKPS<1:0>
Prescaler
F
(/n)
CY
TCKPS<1:0>
TCKPS<1:0>
Prescaler
Prescaler
Sync
Gate
(/n)
(/n)
TCKPS<1:0>
Prescaler
Sync
Gate
Sync
(/n)
family
and
Preliminary
of
Falling Edge
Falling Edge
Detect
Detect
TGATE
TGATE
TCS
TCS
Timer2 and Timer4 are Type B timers with the following
specific features:
• A Type B timer can be concatenated with a Type
• The external clock input (TxCK) is always
A block diagram of the Type B timer is shown in
Figure 13-1.
Timer3 and Timer5 are Type C timers with the following
specific features:
• A Type C timer can be concatenated with a Type
• At least one Type C timer has the ability to trigger
• The external clock input (TxCK) is always syn-
A block diagram of the Type C timer is shown in
Figure 13-2.
C timer to form a 32-bit timer
synchronized to the internal device clock and the
clock synchronization is performed after the
prescaler.
B timer to form a 32-bit timer
an A/D conversion.
chronized to the internal device clock and the
clock synchronization is performed before the
prescaler
10
00
x1
10
00
x1
Comparator
Comparator
TMRx
PRx
TMRx
PRx
Reset
Equal
Equal
Reset
TGATE
1
0
ADC SOC Trigger
TGATE
Set TxIF flag
1
0
DS70291D-page 197
Set TxIF flag