DSPIC33FJ128MC202-I/SP Microchip Technology, DSPIC33FJ128MC202-I/SP Datasheet - Page 290

IC DSPIC MCU/DSP 128K 28DIP

DSPIC33FJ128MC202-I/SP

Manufacturer Part Number
DSPIC33FJ128MC202-I/SP
Description
IC DSPIC MCU/DSP 128K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC202-I/SP

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Package
28SPDIP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit|6-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
REGISTER 23-2:
DS70291D-page 290
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
R/W-0
R/W-0
ROEN
LOEN
LOEN: Left Channel DAC output enable
1 = Positive and negative DAC outputs are enabled
0 = DAC outputs are disabled
Unimplemented: Read as ‘0’
LMVOEN: Left Channel Midpoint DAC output voltage enable
1 = Midpoint DAC output is enabled
0 = Midpoint output is disabled
Unimplemented: Read as ‘0’
LITYPE: Left Channel Type of Interrupt
1 = Interrupt if FIFO is EMPTY
0 = Interrupt if FIFO is NOT FULL
LFULL: Status, Left Channel Data input FIFO is FULL
1 = FIFO is Full
0 = FIFO is not Full
LEMPTY: Status, Left Channel Data input FIFO is EMPTY
1 = FIFO is Empty
0 = FIFO is not Empty
ROEN: Right Channel DAC output enable
1 = Positive and negative DAC outputs are enabled
0 = DAC outputs are disabled
Unimplemented: Read as ‘0’
RMVOEN: Right Channel Midpoint DAC output voltage enable
1 = Midpoint DAC output is enabled
0 = Midpoint output is disabled
Unimplemented: Read as ‘0’
RITYPE: Right Channel Type of Interrupt
1 = Interrupt if FIFO is EMPTY
0 = Interrupt if FIFO is NOT FULL
RFULL: Status, Right Channel Data input FIFO is FULL
1 = FIFO is Full
0 = FIFO is not Full
REMPTY: Status, Right Channel Data input FIFO is EMPTY
1 = FIFO is Empty
0 = FIFO is not Empty
U-0
U-0
DAC1STAT: DAC STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
RMVOEN
LMVOEN
R/W-0
R/W-0
U-0
U-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
RITYPE
LITYPE
R/W-0
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
RFULL
LFULL
R-0
R-0
REMPTY
LEMPTY
R-0
R-0
bit 8
bit 0

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