DSPIC33FJ64GP802-E/SO Microchip Technology, DSPIC33FJ64GP802-E/SO Datasheet - Page 134

IC DSPIC MCU/DSP 64K 28-SOIC

DSPIC33FJ64GP802-E/SO

Manufacturer Part Number
DSPIC33FJ64GP802-E/SO
Description
IC DSPIC MCU/DSP 64K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP802-E/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b, D/A 4x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
10-chx10-bit|10-chx12-bit
On-chip Dac
2-chx16-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-3:
REGISTER 8-4:
DS70292E-page 134
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
R/W-0
R/W-0
R/W-0
R/W-0
A read of this address register returns the current contents of the DMA RAM Address register, not the con-
tents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
A read of this address register returns the current contents of the DMA RAM Address register, not the con-
tents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
STA<15:0>: Primary DMA RAM Start Address bits (source or destination)
STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)
R/W-0
R/W-0
R/W-0
R/W-0
DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A
DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STB<15:8>
STA<15:8>
STA<7:0>
STB<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
© 2011 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1)
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0

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