PIC18LF4331-I/PT Microchip Technology, PIC18LF4331-I/PT Datasheet - Page 232
![IC PIC MCU FLASH 4KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF4331-I/PT
Manufacturer Part Number
PIC18LF4331-I/PT
Description
IC PIC MCU FLASH 4KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(4 pages)
8.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18LF4331-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18LF4331-I/PTR
PIC18LF4331-I/PTR
PIC18LF4331-I/PTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4331-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- Current page: 232 of 392
- Download datasheet (4Mb)
PIC18F2331/2431/4331/4431
20.3.5
The Enhanced USART module has the capability of
sending the special Break character sequences that
are required by the LIN/J2602 bus standard. The Break
character transmit consists of a Start bit, followed by
twelve ‘0’ bits and a Stop bit. The Frame Break charac-
ter is sent whenever the SENDB and TXEN bits
(TXSTA<3> and TXSTA<5>) are set while the Transmit
Shift register is loaded with data. Note that the value of
data written to TXREG will be ignored and all ‘0’s will
be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN/J2602 specification).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See
character sequence.
FIGURE 20-9:
DS39616D-page 232
(Interrupt Reg. Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREG
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
TRMT bit
Figure 20-9
BREAK CHARACTER SEQUENCE
TX (Pin)
TXIF bit
SENDB
SEND BREAK CHARACTER SEQUENCE
for the timing of the Break
Dummy Write
SENDB sampled here
Start Bit
Bit 0
Bit 1
master.
20.3.5.1
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN/J2602 bus
1.
2.
3.
4.
5.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
20.3.6
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 of the typical speed. This allows
for the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the auto-wake-up feature
described in
Break
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
before placing the EUSART in its Sleep mode.
Break
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to setup the
Break character.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
Character”. By enabling this feature, the
RECEIVING A BREAK CHARACTER
Section 20.3.4 “Auto-Wake-up on Sync
Break and Sync Transmit Sequence
Bit 11
Auto-Cleared
2010 Microchip Technology Inc.
Stop Bit
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