PIC18F4550-I/PT Microchip Technology, PIC18F4550-I/PT Datasheet - Page 7
![IC PIC MCU FLASH 16KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4550-I/PT
Manufacturer Part Number
PIC18F4550-I/PT
Description
IC PIC MCU FLASH 16KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18F4550-IP.pdf
(430 pages)
Specifications of PIC18F4550-I/PT
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI/I2C/EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
GPIODM-KPLCD - BOARD DEMO LCD GPIO EXP KEYPADXLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4550-I/PT
Manufacturer:
MURATA
Quantity:
12 000
Company:
Part Number:
PIC18F4550-I/PT
Manufacturer:
Microchip Technology
Quantity:
36 332
Company:
Part Number:
PIC18F4550-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4550-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
11. Module: PORTD
12. Module: Module: MSSP
13. Module: EUSART
bit 4 SCKP: Synchronous Clock Polarity Select bit
© 2008 Microchip Technology Inc.
Each of the PORTD pins has a weak internal pull-up.
A single control bit, RDPU (PORTE<7>), can turn on
all the pull-ups. After the pull-up has been enabled
(PORTE<7> = 1), any access to the PORTE register
would cause the RDPU control bit to clear, except
those that write a '1' to PORTE<7>.
Work around
Reassert RDPU after each and every access to
the PORTE register, except those that write a ‘1’ to
PORTE<7>, or use external pull-ups.
Date Codes that pertain to this issue:
All engineering and production devices.
The I
supported, therefore, SSPCON2 register bits,
ADMSK<5:1>, do not exist in I
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In the BAUDCON register, bits RXDTP and TXCKP
do not exist. BAUDCON bit 4 is defined instead as
SCKP and has the following definition:
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
2
C™ slave address masking feature is not
2
C Slave mode.
PIC18F2455/2550/4455/4550
14. Module: USB
15. Module: MSSP
16. Module: MSSP
The Ping-Pong Buffer mode in which the ping-pong
buffers are enabled for Endpoints 1 to 15
(UCFG<PPB1:PPB0> = 11) is not supported.
Work around
Use other Ping-Pong Buffer modes.
Date Codes that pertain to this issue:
All engineering and production devices.
The MSSP configured in SPI Slave mode will
generate a write collision if SSPBUF is updated and
the previous SSPBUF contents have not been
transferred
Re-initializing the MSSP by clearing and setting the
SSPEN (SSPCON1<5>) bit prior to rewriting
SSPBUF will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify whether the previous contents were
transferred by reading the BF (SSPSTAT<0>) bit. If
the previous byte has not been transferred, update
SSPBUF and clear the WCOL (SSPCON1<7>) bit if
necessary.
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
to the shift register
.
DS80220J-page 7