PIC16F84-04I/SO Microchip Technology, PIC16F84-04I/SO Datasheet - Page 23
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PIC16F84-04I/SO
Manufacturer Part Number
PIC16F84-04I/SO
Description
IC MCU FLASH 1KX14 EE 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16LF84A-04P.pdf
(125 pages)
3.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16F84-04I/SO
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
4MHz
No. Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MIL309-1075 - ADAPTER 18-SOIC TO 18-SOIC309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
5.2
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A ’1’ on
any bit in the TRISB register puts the corresponding
output driver in a hi-impedance mode. A ’0’ on any bit
in the TRISB register puts the contents of the output
latch on the selected pin(s).
Each of the PORTB pins have a weak internal pull-up.
A single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (OPTION_REG<7>) bit.
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The pins value in input mode
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of the pins are
OR’ed
change interrupt.
FIGURE 5-3:
Set RBIF
Data bus
WR TRIS
WR Port
RBPU
1998 Microchip Technology Inc.
Note 1: TRISB = ’1’ enables weak pull-up
(1)
2: I/O pins have diode protection to V
together
PORTB and TRISB Registers
From other
RB7:RB4 pins
(if RBPU = ’0’ in the OPTION_REG register).
BLOCK DIAGRAM OF PINS
RB7:RB4
Data Latch
TRIS Latch
RD TRIS
RD Port
to
D
D
CK
CK
generate
Q
Q
Q
Q
Latch
the
DD
EN
EN
D
D
and V
RD Port
RB
V
SS
P
DD
.
weak
pull-up
TTL
Input
Buffer
pin
port
I/O
(2)
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set the RBIF bit.
Reading PORTB will end the mismatch condition, and
allow the RBIF bit to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (see AN552 in the
Embedded Control Handbook).
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-4:
Data bus
WR TRIS
WR Port
RBPU
RB0/INT
Note 1: TRISB = ’1’ enables weak pull-up
Note 1: For a change on the I/O pin to be
Read (or write) PORTB. This will end the mis-
match condition.
Clear flag bit RBIF.
(1)
2: I/O pins have diode protection to V
(if RBPU = ’0’ in the OPTION_REG register).
recognized, the pulse width must be at
least T
CY
BLOCK DIAGRAM OF PINS
RB3:RB0
RD TRIS
RD Port
Data Latch
TRIS Latch
D
D
(4/f
CK
CK
Schmitt Trigger
Buffer
OSC
Q
Q
) wide.
PIC16F8X
Q
DD
DS30430C-page 23
EN
and V
TTL
Input
Buffer
D
SS
V
.
P
RD Port
DD
weak
pull-up
pin
I/O
(2)