ATMEGA16L-8PU Atmel, ATMEGA16L-8PU Datasheet - Page 209
![IC AVR MCU 16K 8MHZ 3V 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA16L-8PU
Manufacturer Part Number
ATMEGA16L-8PU
Description
IC AVR MCU 16K 8MHZ 3V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA16L-8MI.pdf
(26 pages)
2.ATMEGA16L-8MI.pdf
(357 pages)
3.ATMEGA16-16PU.pdf
(358 pages)
Specifications of ATMEGA16L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
512 Bytes
Input Output
32
Interface
JTAG/SPI/UART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.7-5.5 V
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 209 of 357
- Download datasheet (8Mb)
Differential Gain
Channels
2466T–AVR–07/10
Figure 103. ADC Timing Diagram, Auto Triggered Conversion
Figure 104. ADC Timing Diagram, Free Running Conversion
Table 81. ADC Conversion Time
When using differential gain channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock. This synchronization is done automatically by the ADC interface in such a way that the
sample-and-hold occurs at a specific phase of CK
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
MUX and REFS
Update
1
2
Conversion
Complete
3
One Conversion
Sample & Hold
11
4
Sample & Hold (Cycles
12
5
from Start of
Conversion)
6
1.5/2.5
13
13.5
1.5
2
7
One Conversion
ADC2
Next Conversion
1
MSB of Result
LSB of Result
8
. A conversion initiated by the user (that is,
2
MUX and REFS
Update
9
Conversion
10
3
Complete
Conversion Time (Cycles)
11
Sample & Hold
4
12
ADC2
ATmega16(L)
13/14
13
13.5
25
13
equal to half the ADC
MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
2
209
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