DSPIC30F4013-30I/PT Microchip Technology, DSPIC30F4013-30I/PT Datasheet - Page 9

• Manufacturer Part Number: DSPIC30F4013-30I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-30I/PT

• Program Memory Type: FLASH
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401330IPT

7. Module: 32 kHz Low-Power (LP)
8. Module: DCI
© 2010 Microchip Technology Inc.
The LP oscillator is located on the SOSCO and
SOSCI device pins and serves as a secondary
crystal clock source for low-power operation. The
LP oscillator can also drive Timer1 for a real-time
clock application. The LP oscillator does not
function when the device is placed in Sleep mode.
Work around
If the application needs to wake-up periodically
from Sleep mode using an internal timer, the
Watchdog Timer may be enabled prior to entering
Sleep mode. When the Watchdog Timer expires,
code execution will resume from the instruction
immediately following the SLEEP instruction.
Affected Silicon Revisions
The DCI module is enabled by setting the DCIEN bit
(DCICON1<15>) and disabled by clearing the
DCIEN bit. Once enabled, if the DCI module is
subsequently disabled by the application, the
module does not release the ownership of the
COFS, CSCK, CSDI and CSDO pins to the
associated port functions (RB9, RB10, RB11 and
RB12).
Work around
After disabling the DCI module by clearing the
DCIEN bit, the application should further set the
DCI Module Disable bit, DCIMD (PMD1<8>). The
port functions associated with the DCI module
(RB9, RB10, RB11 and RB12) may now be used.
Affected Silicon Revisions
A1
A1
X
X
A2
A2
X
Oscillator
9. Module: Output Compare
10. Module: Output Compare
If the desire duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
The second problem is that on the next cycle after
the glitch, the OC pin does not go high, or in other
words, it misses the next compare for any value
written on OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
Affected Silicon Revisions
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The Output Compare module is configured and
When these events occur, the Output Compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a timer interrupt
and write to the associated PORT register to
control the pin manually.
Affected Silicon Revisions
A1
A1
high using the Output Compare module or a
write to the associated PORT register.
enabled to drive the pin low at some point in later
time (OCxCON = 0x0002 or OCxCON = 0x0003).
X
X
register when operating n PWM mode. In this
case, no 0% duty cycle is achievable.
Output Compare module can be disabled
for 0% duty cycles, and re-enabled for
non-zero percent duty cycles.
CY
dsPIC30F3014/4013
A2
A2
X
X
) after the module is enabled.
DS80455D-page 9
CY
.