PIC18F4550-I/ML Microchip Technology, PIC18F4550-I/ML Datasheet - Page 308
![IC PIC MCU FLASH 16KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4550-I/ML
Manufacturer Part Number
PIC18F4550-I/ML
Description
IC PIC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18F4550-IP.pdf
(430 pages)
Specifications of PIC18F4550-I/ML
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
EAUSART/I2C/MSSP/SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
GPIODM-KPLCD - BOARD DEMO LCD GPIO EXP KEYPADXLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- PIC18F4550-IP PDF datasheet #7
- Current page: 308 of 430
- Download datasheet (8Mb)
PIC18F2455/2550/4455/4550
Even when the dedicated port is enabled, the ICSP and
ICD functions remain available through the legacy port.
When V
of the ICRST/ICV
25.9.2
PIC18F4455/4550 devices in 44-pin TQFP packages
also have the ability to change their configuration under
external control for debugging purposes. This allows
the device to behave as if it were a PIC18F2455/2550
28-pin device.
This 28-pin Configuration mode is controlled through a
single pin, NC/ICPORTS. Connecting this pin to V
forces the device to function as a 28-pin device.
Features normally associated with the 40/44-pin
devices are disabled along with their corresponding
control registers and bits. This includes PORTD and
PORTE, the SPP and the Enhanced PWM functionality
of CCP1. On the other hand, connecting the pin to V
forces the device to function in its default configuration.
The configuration option is only available when back-
ground debugging and the dedicated ICD/ICSP port
are both enabled (DEBUG Configuration bit is clear
and ICPRT Configuration bit is set). When disabled,
NC/ICPORTS is a No Connect pin.
25.10 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP) . When Single-Supply Program-
ming
programmed without requiring high voltage being
applied
RB5/KBI1/PGM pin is then dedicated to controlling
Program mode entry and is not available as a general
purpose I/O pin.
While programming using Single-Supply Program-
ming, V
normal execution mode. To enter Programming mode,
V
DS39632C-page 306
DD
Note 1: The ICPRT Configuration bit can only be
is applied to the PGM pin.
is
IH
DD
2: The ICPRT Configuration bit must be
to
is seen on the MCLR/V
is applied to the MCLR/V
enabled,
28-PIN EMULATION
programmed through the default ICSP
port.
maintained clear for all 28-pin and 40-pin
devices; otherwise, unexpected operation
may occur.
the
PP
pin is ignored.
MCLR/V
the
microcontroller
PP
/RE3
PP
/RE3 pin, the state
PP
pin,
/RE3 pin as in
but
can
Preliminary
the
DD
be
SS
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (V
MCLR/V
only the standard high-voltage programming is
available and must be used to program the device.
Memory that is not code-protected can be erased using
either a Block Erase, or erased row by row, then written
at any specified V
erased, a Block Erase is required. If a Block Erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with V
Note 1: High-Voltage Programming is always
PP
2: While in Low-Voltage ICSP Programming
3: When using Low-Voltage ICSP Program-
4: If the device Master Clear is disabled,
/RE3 pin). Once LVP has been disabled,
available, regardless of the state of the
LVP bit, by applying V
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and should
be held low during normal operation.
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
b) make certain that RB5/KBI1/PGM
(CONFIG4L<2> = 0); or
is held low during entry into ICSP.
DD
. If code-protected memory is to be
© 2006 Microchip Technology Inc.
IHH
IHH
DD
to the MCLR pin.
applied to the
of 4.5V to 5.5V.
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