PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 196

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39026C-page 194
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Carry bit= 1
REG
WREG
Carry bit= 0
REG
WREG
Q1
=
=
=
=
register ’f’
ADD WREG and Carry bit to f
[ label ] ADDWFC
0
d
a
(WREG) + (f) + (C)
N,OV, C, DC, Z
Add WREG, the Carry Flag and data
memory location ’f’. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in data memory
location 'f'. If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden.
1
1
ADDWFC
Read
Q2
0010
0x02
0x4D
0x02
0x50
f
[0,1]
[0,1]
255
00da
REG, 0, 1
Process
Data
Q3
ffff
f [,d [,a]
dest
destination
Write to
Q4
ffff
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WREG
WREG
Q1
Read literal
=
=
AND literal with WREG
[ label ] ANDLW
0
(WREG) .AND. k
N,Z
The contents of WREG are ANDed
with the 8-bit literal 'k'. The result is
placed in WREG.
1
1
ANDLW
0000
Q2
’k’
0xA3
0x03
k
2001 Microchip Technology Inc.
255
1011
0x5F
Process
Data
Q3
k
kkkk
WREG
Write to
WREG
Q4
kkkk