DSPIC30F4013-20I/P Microchip Technology, DSPIC30F4013-20I/P Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F4013-20I/P
• Description: IC DSPIC MCU/DSP 48K 40DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/P

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F4013-20IP

dsPIC30F3014/4013
TABLE 2:
DS80455D-page 2
Operations
Note 1:
INT0, ADC
and Sleep
Controller
Oscillator
Compare
Compare
Interrupt
Module
32 kHz
Output
Output
Power
Mode
I
CPU
CPU
CPU
CPU
Low-
PSV
(LP)
2
DCI
PLL
PLL
I/O
C™
Only those issues indicated in the last column apply to the current silicon revision.
Modification
Sleep Mode
Sleep Mode
PWM Mode
Instructions
SFR Writes
Instruction
Instruction
Nested DO
MAC Class
Port Pins
4x Mode
8x Mode
SDA Pin
Feature
Address
SILICON ISSUE SUMMARY
with ±4
DAW.b
Loops
DISI
—
—
—
Number
Item
13.
10.
11.
12.
14.
15.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification, will cause an address
error trap.
The Decimal Adjust instruction, DAW.b, may improperly clear
the Carry bit, C (SR<0>).
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV) will
corrupt specific bits in the STATUS Register, SR.
An interrupt occurring immediately after modifying the CPU IPL,
interrupt IPL, interrupt enable or interrupt flag may cause an
address error trap.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
When using two DO loops in a nested fashion, terminating the
inner-level DO loop by setting the EDT bit (CORCON<11>) will
produce unexpected results.
The LP oscillator does not function when the device is placed in
Sleep mode.
Once enabled, if the DCI module is subsequently disabled by
the application, the module does not release the ownership of
the COFS, CSCK, CSDI and CSDO pins to the associated port
functions (RB9, RB10, RB11 and RB12).
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after the
glitch.
The Output Compare module will produce a glitch on the output
when an I/O pin is initially set high and the module is configured
to drive the pin low at a specified time.
Writes to certain unimplemented address locations can affect I/
O Port register values.
The 4x PLL mode of operation may not function correctly for
certain input frequencies.
The data pin (SDA) on the I
the LATF<2> bit is low.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep mode if the SMPI bits are non-zero.
If 8x PLL mode is used, the input frequency range is 5 MHz-10
MHz instead of 4 MHz-10 MHz.
Issue Summary
2
C module does not function unless
© 2010 Microchip Technology Inc.
Revisions
A1
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)