DSPIC30F4011-30I/P Microchip Technology, DSPIC30F4011-30I/P Datasheet - Page 2
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DSPIC30F4011-30I/P
Manufacturer Part Number
DSPIC30F4011-30I/P
Description
IC DSPIC MCU/DSP 48K 40DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F4012-30ISO.pdf
(238 pages)
3.DSPIC30F4012-30ISO.pdf
(18 pages)
4.DSPIC30F4012-30ISO.pdf
(6 pages)
5.DSPIC30F4012-30ISO.pdf
(16 pages)
6.DSPIC30F4012-30ISO.pdf
(22 pages)
7.DSPIC30F4011-30IP.pdf
(228 pages)
Specifications of DSPIC30F4011-30I/P
Program Memory Type
FLASH
Program Memory Size
48KB (16K x 24)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F4011-30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4011-30I/P
Manufacturer:
CJ
Quantity:
600 000
Part Number:
DSPIC30F4011-30I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F4011-30I/PT
Manufacturer:
ATMEL
Quantity:
3 000
Company:
Part Number:
DSPIC30F4011-30I/PT
Manufacturer:
MICROCHIP
Quantity:
455
Company:
Part Number:
DSPIC30F4011-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F4011-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F4011/4012
10. Output Compare Module
11. INT0, ADC and Sleep Mode
12. 8x PLL Mode
13. 10-bit ADC: Sampling Rate
14. Quadrature Encoder Interface (QEI) Module
15. I
16. I
17. I
DS80398A-page 2
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero.
If 8x PLL mode is used, the input frequency range
is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
The 10-bit Analog-to-Digital Converter (ADC) has
a maximum sampling rate of 750 ksps.
The QEI module does not generate an interrupt in
a particular overflow condition.
The I
operating as an I
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the least
significant bits of the address are the same as the
7-bit reserved addresses.
2
2
2
C™ Module
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
2
C module loses incoming data bytes when
2
C module is configured for 10-bit
2
C devices, the A10 and A9 bits may
2
C slave.
18. I
19. I
20. Motor Control PWM – PWM Counter Register
21. I/O Port – Port Pin Multiplexed with IC1
22. Timer Module
23. PLL Lock Status Bit
24. PSV Operations
The following sections describe the errata and work
around to these errata, where they may apply.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
PTMR does not continue counting down after
halting code execution in Debug mode.
The Port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
Clock switching prevents the device from waking
up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
2
2
C Module: 10-bit Addressing Mode
C Module
2
2
C module is enabled, the dsPIC
C module is configured as a 10-bit
© 2008 Microchip Technology Inc.
®
DSC