PIC18LF2320-I/SP Microchip Technology, PIC18LF2320-I/SP Datasheet - Page 300
![IC MCU FLASH 4KX16 EEPROM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2320-I/SP
Manufacturer Part Number
PIC18LF2320-I/SP
Description
IC MCU FLASH 4KX16 EEPROM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2220-ISO.pdf
(394 pages)
3.PIC18F2220-ISO.pdf
(6 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(8 pages)
6.PIC18F2220-ISO.pdf
(6 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18LF2320-I/SP
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2220-ISO PDF datasheet #2
- PIC18F2220-ISO PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- Current page: 300 of 394
- Download datasheet (7Mb)
PIC18F2220/2320/4220/4320
TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39599G-page 298
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC = Address (HERE)
If CNT
PC
If CNT
PC
No
No
No
Q1
Q1
Q1
register ‘f’
operation
operation
operation
Test f, Skip if 0
[ label ] TSTFSZ f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
skip if f = 0
None
If ‘f’ = 0, the next instruction,
fetched during the current instruc-
tion execution is discarded and a
NOP is executed, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
=
=
≠
=
by a 2-word instruction.
0x00,
Address (ZERO)
0x00,
Address (NZERO)
:
TSTFSZ
:
011a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
CNT
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
literal ‘k’
[ label ] XORLW k
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
The contents of W are XOR’ed
with the 8-bit literal ‘k’. The result
is placed in W.
1
1
XORLW 0xAF
Exclusive OR Literal with W
Read
Q2
0000
0xB5
0x1A
© 2007 Microchip Technology Inc.
1010
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
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