PIC18F2610-I/SP Microchip Technology, PIC18F2610-I/SP Datasheet - Page 4

• Manufacturer Part Number: PIC18F2610-I/SP
• Description: IC MCU FLASH 32KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2610-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3968 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2515/2610/4515/4610 FAMILY
5. Module: Master Synchronous Serial Port
DS80416A-page 4
When configured for I
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read within a window after the SSPIF interrupt
(PIR1<3>) has occurred.
Work around
The issue can be resolved either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Date Codes that pertain to this issue:
All engineering and production devices.
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
is
(MSSP)
done
2
C slave reception, enable the
by
2
C™ slave reception, the
setting
the
SEN
bit
6. Module: Enhanced Universal
1.
2.
3.
4.
5.
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTA<7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2 T
Disable
PIE1<5> = 0).
Disable the EUSART (RCSTA<7> = 0).
Re-enable the EUSART (RCSTA<7> = 1).
Re-enable Receive Interrupts (PIE1<5> = 1).
(This is the first T
Execute a NOP instruction.
(This is the second T
Date Codes that pertain to this issue:
All engineering and production devices.
RCSTA<7> = 0)
CY
Synchronous Receiver
Transmitter (EUSART)
Receive
delay after re-enabling the EUSART.
CY
© 2008 Microchip Technology Inc.
delay.)
CY
Interrupts
delay.)
(RCIE
bit,