PIC18F252-I/SO Microchip Technology, PIC18F252-I/SO Datasheet - Page 222

IC MCU FLASH 16KX16 EE 28SOIC

PIC18F252-I/SO

Manufacturer Part Number
PIC18F252-I/SO
Description
IC MCU FLASH 16KX16 EE 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F252-I/SO

Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
23
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
PIC18F252-I/SOG
PIC18F252-I/SOG
PIC18F252I/SO

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PIC18F252-I/SO
0
PIC18FXX2
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39564C-page 220
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG = 0xC7
FLAG_REG = 0x47
Q1
register 'f'
Bit Clear f
[ label ] BCF
0
0
a
0
None
Bit 'b' in register 'f' is cleared. If ‘a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1
BCF
Read
1001
Q2
f
b
[0,1]
f<b>
255
7
FLAG_REG,
bbba
Process
Data
Q3
f,b[,a]
ffff
7, 0
register 'f'
Write
Q4
ffff
BN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Negative
If Negative
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Negative
[ label ] BN
-128
if negative bit is ’1’
(PC) + 2 + 2n
None
If the Negative bit is ’1’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
'n'
'n'
=
=
=
=
=
© 2006 Microchip Technology Inc.
n
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
127
0110
operation
BN
Process
Process
Data
Data
n
No
Q3
Q3
PC
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn

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