PIC18F252-I/SP Microchip Technology, PIC18F252-I/SP Datasheet - Page 138
![IC MCU FLASH 16KX16 EE 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F252-I/SP
Manufacturer Part Number
PIC18F252-I/SP
Description
IC MCU FLASH 16KX16 EE 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18F452-EP.pdf
(332 pages)
Specifications of PIC18F252-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
23
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC18F252-I/SPG
PIC18F252-I/SPG
PIC18F252I/SP
PIC18F252-I/SPG
PIC18F252I/SP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F252-I/SP
Manufacturer:
PANASONIC
Quantity:
35 000
Company:
Part Number:
PIC18F252-I/SP
Manufacturer:
MICP0CRIP
Quantity:
5 510
Part Number:
PIC18F252-I/SP
Manufacturer:
MIC
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18F452-EP PDF datasheet #7
- Current page: 138 of 332
- Download datasheet (6Mb)
PIC18FXX2
REGISTER 15-4:
DS39564B-page 136
bit 7
bit 6
bit 5
bit 4
bit 3-0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1000 = I
0111 = I
0110 = I
Legend:
R = Readable bit
- n = Value at POR
SSPCON1: MSSP CONTROL REGISTER1 (I
WCOL
R/W-0
Note:
Note:
a transmission to be started (must be cleared in software)
cleared in software)
be cleared in software)
2
2
2
2
2
2
C Slave mode, 10-bit address with START and STOP bit interrupts enabled
C Slave mode, 7-bit address with START and STOP bit interrupts enabled
C Firmware Controlled Master mode (Slave IDLE)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
When enabled, the SDA and SCL pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved, or implemented in
SPI mode only.
SSPOV
R/W-0
W = Writable bit
’1’ = Bit is set
SSPEN
R/W-0
OSC
R/W-0
CKP
/ (4 * (SSPADD+1))
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPM3
R/W-0
2
C MODE)
2
SSPM2
C conditions were not valid for
R/W-0
2002 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
SSPM0
R/W-0
bit 0
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