DSPIC33FJ128GP706A-I/PT Microchip Technology, DSPIC33FJ128GP706A-I/PT Datasheet - Page 21

• Manufacturer Part Number: DSPIC33FJ128GP706A-I/PT
• Description: IC DSPIC MCU/DSP 128K 64-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706A-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 36-chx10-bit|36-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Hardware Description
2.3.1
Samples And Processing
Input capture IC
on the dsPIC33F is used to detect if A/D conversion is complete.
1
However, not all MCP3909 device samples are stored in the MCU, depending on the
parameter being calculated. The ADC conversion rate of the MCP3909 device is
determined by the frequency of the master clock (3.378 MHz for the case of a 50 Hz
line), and the output data rate is MCLK/256 or 12.8 ksps. After each conversion is
complete, a Data Ready signal is generated by the SDO of the MCP3909 device. The
signal is fed into IC
, allowing the Interrupt Service Routine (ISR) of IC
to read the
1
1
data. When the MCP3909 device outputs data, it first sends an ADC result of the
voltage channel, then an ADC result of the current channel, with MSB first.
As noted, not all MCP3909 device samples are used for calculating all the parameters.
In practice, 6.4 ksps sampling rate is required, which means only 1 output data is used
for every 2 data sampled. For 50 Hz input signal, 6.4 ksps sampling rate will take 128
samples for each cycle. For example, the active power metering is computed based on
this condition.
But for other parameters for which precision is not critical, such as reactive energy,
voltage, current and frequency, the sampling rate may be reduced to save data storage
space and processing time. In this design, the 3.2 ksps sampling rate is used, which
means only 1 result is stored for every 4 ADC conversions.
After each conversion, a positive pulse with the width of 4 clock cycles is output by the
SDO pin of the MCP3909 device. IC
is used to detect the falling edge of the pulse and
1
generate an interrupt for every 2 falling edges, i.e., 1 data is read for every 2 conver-
sions, thus realizing 6.4 ksps sampling rate.
© 2009 Microchip Technology Inc.
DS51723A-page 21