PIC24HJ64GP510-I/PF Microchip Technology, PIC24HJ64GP510-I/PF Datasheet - Page 154

• Manufacturer Part Number: PIC24HJ64GP510-I/PF
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP510-I/PF

• Core Size: 16-Bit
• Program Memory Size: 64KB (22K x 24)
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• No. Of Pwm Channels: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24H
To set up the SPI module for the Slave mode of operation:
1.
2.
3.
4.
FIGURE 15-1:
DS70175C-page 152
Clear the SPIxBUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 0.
Clear the SMP bit.
SDOx
SCKx
SDIx
SSx
Clear the SPIxIF bit in the respective IFSn
register.
Set the SPIxIE bit in the respective IECn
register.
Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
Read SPIxBUF
Control
Sync
Transfer
registers
SPI MODULE BLOCK DIAGRAM
SPIxRXB
bit 0
SPIxBUF
SPIxSR
with
Control
Clock
Shift Control
SPIxTXB
MSTEN
Transfer
Write SPIxBUF
Preliminary
Select
Edge
5.
6.
7.
The SPI module generates an interrupt indicating com-
pletion of a byte or word transfer, as well as a separate
interrupt for all SPI error conditions.
16
Note:
If the CKE bit is set, then the SSEN bit
(SPIxCON1<7>) must be set to enable the SSx
pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Secondary
1:1 to 1:8
Prescaler
Internal Data Bus
Both SPI1 and SPI2 can trigger a DMA
data transfer. If SPI1 or SPI2 is selected
as the DMA IRQ source, a DMA transfer
occurs when the SPI1IF or SPI2IF bit gets
set as a result of an SPI1 or SPI2 byte or
word transfer.
1:1/4/16/64
Prescaler
Primary
© 2006 Microchip Technology Inc.
F
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
CY