PIC16C72-20I/SP Microchip Technology, PIC16C72-20I/SP Datasheet - Page 6

• Manufacturer Part Number: PIC16C72-20I/SP
• Description: IC MCU OTP 2KX14 A/D PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72-20I/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16C72 Series
2.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM.
All implemented banks contain special function regis-
ters. Some “high use” special function registers from
one bank may be mirrored in another bank for code
reduction and quicker access (ex; the STATUS register
is in Bank 0 and Bank 1).
2.2.1
The register file can be accessed either directly or indi-
rectly
(Section 2.5).
DS39016A-page 6
RP1*
= 00
= 01
= 10
= 11
*
Maintain this bit clear to ensure upward com-
patibility with future products.
through
Data Memory Organization
GENERAL PURPOSE REGISTER FILE
RP0
Bank0
Bank1
Bank2 (not implemented)
Bank3 (not implemented)
(STATUS<6:5>)
the
File
Select
Register
FSR
Preliminary
FIGURE 2-2:
Note 1: Not a physical register.
Address
File
0Ch
0Dh
1Ch
1Dh
0Ah
0Bh
0Eh
1Ah
1Bh
1Eh
Unimplemented data memory locations, read as '0'.
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
10h
12h
13h
14h
15h
16h
17h
18h
19h
1Fh
7Fh
20h
11h
CCP1CON
SSPCON
CCPR1H
ADCON0
SSPBUF
PCLATH
INTCON
CCPR1L
STATUS
PORTB
PORTC
TMR1H
ADRES
INDF
PORTA
TMR1L
T1CON
T2CON
Bank 0
TMR0
TMR2
PIR1
Purpose
Register
General
PCL
FSR
REGISTER FILE MAP
(1)
1998 Microchip Technology Inc.
SSPSTAT
SSPADD
ADCON1
Purpose
Register
OPTION
STATUS
PCLATH
INTCON
General
Bank 1
INDF
TRISA
TRISB
TRISC
PCON
PIE1
FSR
PCL
PR2
(1)
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
FFh
File