PIC18F4553-I/P Microchip Technology, PIC18F4553-I/P Datasheet - Page 2

• Manufacturer Part Number: PIC18F4553-I/P
• Description: IC PIC MCU FLASH 16KX16 40-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4553-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 34
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: MSSP/I2C/SPI/EUSART/CCP/ECCP
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163025 - PIC DEM FULL SPEED USB DEMO BRD444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2458/2553/4458/4553
2. Module: MSSP
3. Module: ECCP (PWM Mode)
DS80323D-page 2
With MSSP in SPI Master mode, F
Timer2/2 clock rate and CKE = 0, a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit, SSPIF, is set or
the Buffer Full bit, BF, is set and before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents. Verify the WCOL
bit is clear after writing SSPBUF. If the WCOL is
set, clear the bit in software and rewrite the
SSPBUF register.
Date Codes that pertain to this issue:
All engineering and production devices.
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM
output may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• A non-zero dead-band delay is specified
• The duty cycle has a value of 0 through 3, or
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
(PDC6:PDC0 > 0)
4n + 3 (n ≥ 1)
OSC
/64 or
4. Module: EUSART
5. Module: ADC
6. Module: Electrical Characteristics (BOR)
In Synchronous Master mode, while transmitting
the Most Significant data bit, the data line (DT) may
change state before the bit finishes transmitting. If
the receiver samples the data line later than 0.5 bit
times + 1.5 T
edge of the MSb, the bit may be read incorrectly.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
When the A/D clock source is selected as 2 T
or RC (ADCS2:ADCS0 = 000 or x11), the E
(Integral Linearity Error) and E
Linearity Error) may exceed the data sheet
specification at codes 2047, 2048 and 2049 only.
Work around
Select a different A/D clock source (4 T
8 T
selecting the 2 T
Date Codes that pertain to this issue:
All engineering and production devices.
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the device data sheet (parameter D005).
The BOR threshold has been observed to increase
with high device operating frequencies, some table
read operations and heavy loading on the USB
voltage regulator. When all of these conditions are
present, BOR has been observed with V
20 percent higher than the V
for a given <BORV1:BORV0> setting.
The BOR threshold may decrease under other
conditions, such as during Sleep, where it may not
occur until V
minimums.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
OSC
, 16 T
CY
OSC
DD
OSC
(of the master) after the starting
, 32 T
is 120 mV below the specified
© 2008 Microchip Technology Inc.
or RC modes.
OSC
, 64 T
BOR
OSC
value specified
DL
) and avoid
(Differential
OSC
OSC
DD
IL
,