AT89C51CC03C-S3RIM Atmel, AT89C51CC03C-S3RIM Datasheet - Page 132
AT89C51CC03C-S3RIM
Manufacturer Part Number
AT89C51CC03C-S3RIM
Description
IC 8051 MCU FLASH 64K 52PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-S3RIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CS3RTR
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Registers
Serial Peripheral Control
Register (SPCON)
132
AT89C51CC03
Figure 62. SPI Interrupt Requests Generation
Three registers in the SPI module provide control, status and data storage functions.
These registers are describe in the following paragraphs.
•
•
•
•
•
•
Table 92 describes this register and explains the use of each bit
Table 92. SPCON Register
SPCON - Serial Peripheral Control Register (0D4H)
Bit Number
SPR2
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
7
7
6
5
4
SPEN
6
Bit Mnemonic
MODFIE
SPTEIE
MODF
SPTE
SPIF
SSDIS
MSTR
SPR2
SPEN
SSDIS
5
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and
SPR0 for detail).
Serial Peripheral Enable
Cleared to disable the SPI interface (internal reset of the SPI).
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
MSTR
4
CPOL
3
.
CPHA
CPU Interrupt Request
2
SPI
4182E–CAN–05/04
SPR1
1
SPR0
0
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