AT89C51CC03C-S3RIM Atmel, AT89C51CC03C-S3RIM Datasheet - Page 54
AT89C51CC03C-S3RIM
Manufacturer Part Number
AT89C51CC03C-S3RIM
Description
IC 8051 MCU FLASH 64K 52PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-S3RIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CS3RTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Power Down Request
Reading the Flash Spaces
User
Extra Row
Hardware Security Byte
Flash Protection from Parallel
Programming
54
AT89C51CC03
Before entering in Power Down (Set bit PD in PCON register) the user should check that
no write sequence is in progress (check BUSY=0), then check that the column latches
are reset (FLOAD=0 in FSTA register. Launch a reset column latches to clear FLOAD if
necessary.
The following procedure is used to read the User space:
•
Note:
The following procedure is used to read the Extra Row space and is summarized in
Figure 28:
•
•
•
The following procedure is used to read the Hardware
summarized in Figure 28:
•
•
Figure 28. Clear FCON to unmap the Hardware Security Byte.Reading Procedure
The three lock bits in Hardware Security Byte (see "In-System Programming" section)
are programmed according to Table 17 provide different level of protection for the on-
chip code and data located in FM0 and FM1.
The only way to write this bits are the parallel mode. They are set by default to level 4
Read one byte in Accumulator by executing MOVC A,@A+DPTR with
A+DPTR=read@.
Map the Extra Row space by writing 02h in FCON register.
Read one byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and
DPTR = FF80h to FFFFh.
Clear FCON to unmap the Extra Row.
Map the Hardware Security space by writing 04h in FCON register.
Read the byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and
DPTR = 0000h.
FCON is supposed to be reset when not needed.
Exec: MOVC A, @A+DPTR
Flash Spaces Reading
Flash Spaces Mapping
FCON= 00000xx0b
DPTR= Address
FCON = 00h
Clear Mode
Data Read
ACC= 0
Security
4182E–CAN–05/04
space and is
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