PIC32MX360F256L-80I/PT Microchip Technology, PIC32MX360F256L-80I/PT Datasheet - Page 337

• Manufacturer Part Number: PIC32MX360F256L-80I/PT
• Description: IC PIC MCU FLASH 256K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F256L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (256K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.4.1
In this mode, the timer clock source can only be the
internal
(T1CON<1>) = 0. The T1CK pin provides the gating
mechanism to enable and disable the timer counting,
TGATE (T1CON<7>) = 1. Clock synchronization is not
required, therefore Timer1 synchronization bit, TSYNC
(T1CON<2>), is ignored. The 16-bit TMR1 Count reg-
ister is enabled on the rising edge of the T1CK pin and
increments on every internal PBCLK cycle when the
timer clock prescale <TCKPS> is 1:1.
The timer increments until the TMR1 Count register
matches the PR1 register value. The TMR1 Count reg-
ister resets to 0x0000 on the next PBCLK clock cycle.
A timer match event is not generated. The timer con-
tinues to increment and repeat the period match until
the falling edge of the T1CK pin or the timer is disabled.
On the falling edge of the gate signal, a timer gate
event is generated and the TMR1 Count register stops
counting, but is not reset to 0x0000. The TMR1 Count
register must be reset in software. For further details
regarding
Section 13.5 “Timer Interrupts”.
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMR1
Count register increments on every Nth PBCLK clock
cycle. For further details regarding timer prescaler,
refer to Section 13.4.2 “Timer Clock Prescaler”.
The following steps should be performed to properly
configure the Timer1 peripheral for Gated Timer mode
operation:
1.
2.
3.
4.
5.
6.
7.
8.
© 2008 Microchip Technology Inc.
Clear control bit, ON (T1CON<15>) = 0, to
disable Timer1.
Select the desired timer prescaler using bits,
TCKPS<1:0> (T1CON<5:4>).
Set control bit, TCS (T1CON<1>) = 0, to select
the internal clock source.
Set control bit TGATE (T1CON<6>) = 1.
Clear Timer register, TMR1.
Load Period register, PR1, with desired
16-bit match value.
If timer interrupts are used, refer to Section 13.5
“Timer Interrupts” for interrupt configuration
steps.
Set control bit ON, (T1CON<15>) = 1, to enable
Timer1.
PBCLK
Synchronous Internal Gated Timer
timer
(Peripheral
events
and
Bus
interrupts,
Cock),
Advance Information
TCS
see
EXAMPLE 13-4:
13.4.2
Timer
(T1CON<5:4>), are used to divide the timer clock
source, permitting the TMR register to increment on
every 1, 8, 64, or 256
cycles. For example, if the clock prescale is 1:8, then
the timer increments on every 8th timer clock cycle.
Associated with the clock prescale selection bits is a
prescale counter. This prescale counter is cleared
when any of the following conditions occur:
• Any device Reset, except a Power-on Reset
• The timer is disabled
• A write to the TMR register
• When the timer clock source is external and the
• After a timer match event (TMR1 = PR1) and
T1CON = 0x0;
T1CON = 0x0060;
TMR1 = 0x0;
PR1 = 0xFFFF;
T1CONSET = 0x8000;// Start Timer
Note:
timer clock prescale = N (other than 1:1), 2 to 3
external clock cycles are required, after the timer
ON bit is set = 1, before the TMR1 Count register
increments.
depending on the timer clock prescale setting N
(other than 1:1), the timer will require N/2 addi-
tional (PBCLK or external) clock cycles before the
TMR1 Counter register reset to 0x0000. Reading
the TMR1 Count register just after the timer match
event, but before the TMR1 Count register is rest,
will return the timer match value.
PIC32MX FAMILY
clock
TIMER CLOCK PRESCALER
When the timer clock source is external
and the timer clock prescale = N (other
than 1:1), 2 to 3 external clock cycles are
required to reset and synchronize the
prescaler.
prescale
SYNCHRONOUS
INTERNAL GATED TIMER
INITIALIZATION
// Stop Timer and reset
// Enable gated mode,
// prescaler at 1:64,
// internal clock source
// Load period register
// Clear timer register
(PBCLK or external) clock
bits,
DS61143B-page 335
TCKPS<1:0>