PIC32MX360F256L-80I/PT Microchip Technology, PIC32MX360F256L-80I/PT Datasheet - Page 526
![IC PIC MCU FLASH 256K 100-TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC32MX360F256L-80I/PT
Manufacturer Part Number
PIC32MX360F256L-80I/PT
Description
IC PIC MCU FLASH 256K 100-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F032H-40IPT.pdf
(626 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX360F256L-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
100-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5 x 16 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
No. Of I/o's
85
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
6
Embedded Interface Type
EUART, I2C, PSP, SPI
No. Of Pwm Channels
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Price
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Part Number:
PIC32MX360F256L-80I/PT
Manufacturer:
Microchip Technology
Quantity:
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PIC32MX360F256L-80I/PT
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Quantity:
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Quantity:
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- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- PIC32MX320F032H-40IPT PDF datasheet #6
- PIC32MX320F064H-40IMR PDF datasheet #7
- Current page: 526 of 626
- Download datasheet (9Mb)
PIC32MX FAMILY
23.6.1
The PB
save additional power when the device is in a low activ-
ity mode. The following issues need to be taken into
account when scaling the PBCLK:
• All the peripherals clocked from PBCLK will scale
• Any communication through a peripheral on the
The following steps are recommended if the user
intends to scale the PBCLK divisor dynamically:
• Disable all communication peripherals whose
EXAMPLE 23-2:
DS61143B-page 524
at the same ratio, at the same time. This needs to
be accounted in peripherals which need to main-
tain a constant baud rate, or pulse period even in
low-power modes.
peripheral bus that is in progress when the
PBCLK changes may cause a data or protocol
error due to a frequency change during
transmission or reception.
// Code example to change the PBCLK divisor
// This example is for a device running at 40 MHz
// Make sure that there is no UART send/receive in progress
... user code ...
U1BRG = 0x81;
... user code ...
OSCCONCLR = 0x3 << 19;
... user code ...
// Change Peripheral Clock value
U1BRG = 0x0F;
OSCCONSET = 0x3 << 19;
// Reset Peripheral Clock
OSCCONCLR = 0x3 << 19;
U1BRG = 0x81;
CLK
DYNAMIC PERIPHERAL BUS
SCALING METHOD
can be scaled dynamically, by software, to
CHANGING THE PB CLOCK DIVISOR
// set baud rate for UART1 for 9600
// set PB divisor to minimum (1:1)
// set baud rate for UART1 for 9600 based on
// new PB clock frequency
// set PB divisor to maximum (1:8)
// set PB divisor to minimum (1:1)
// restore baud rate for UART1 to 9600 based
// on new PB clock frequency
Advance Information
• Update the Baud Rate Generator (BRG) settings
• Change the peripheral bus ratio to the desired
• Enable all communication peripherals whose
baud rate will be affected. Care should be taken to
ensure that no communication is currently in
progress before disabling the peripherals as it
may result in protocol errors.
for peripherals as required for operation at the
new PBCLK frequency.
value.
baud rate were affected.
Note:
Modifying the peripheral baud rate is done
by writing to the associated peripheral
SFRs. To minimize latency, the peripher-
als should be modified in the mode where
the PBCLK is running at its highest
frequency.
© 2008 Microchip Technology Inc.
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